Commit a31cf51b authored by Wolfram Sang's avatar Wolfram Sang Committed by Geert Uytterhoeven
Browse files

clk: renesas: rcar-gen3: Add dummy SDnH clock 



Currently, SDnH is handled together with SDn. This caused lots of
problems, so we want SDnH as a separate clock. Introduce a dummy SDnH
type here which creates a fixed-factor clock with factor 1. That allows
us to convert the per-SoC CPG drivers while keeping the old behaviour
for now. A later patch then will add the proper functionality.

Signed-off-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211110191610.5664-2-wsa+renesas@sang-engineering.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 16145013

drivers/clk/renesas/rcar-cpg-lib.c

+9 −0
Original line number Diff line number Diff line
@@ -65,6 +65,15 @@ void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, 
/*

 * SDn Clock

 */



struct clk * __init cpg_sdh_clk_register(const char *name,

	void __iomem *sdnckcr, const char *parent_name,

	struct raw_notifier_head *notifiers)

{

	/* placeholder during transition */

	return clk_register_fixed_factor(NULL, name, parent_name, 0, 1, 1);

}



#define CPG_SD_STP_HCK		BIT(9)

#define CPG_SD_STP_CK		BIT(8)

drivers/clk/renesas/rcar-cpg-lib.h

+4 −0
Original line number Diff line number Diff line
@@ -26,6 +26,10 @@ void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, 


void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set);



struct clk * __init cpg_sdh_clk_register(const char *name,

	void __iomem *sdnckcr, const char *parent_name,

	struct raw_notifier_head *notifiers);



struct clk * __init cpg_sd_clk_register(const char *name,

	void __iomem *base, unsigned int offset, const char *parent_name,

	struct raw_notifier_head *notifiers, bool skip_first);

drivers/clk/renesas/rcar-gen3-cpg.c

+4 −0
Original line number Diff line number Diff line
@@ -401,6 +401,10 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, 
			mult *= 2;

		break;



	case CLK_TYPE_GEN3_SDH:

		return cpg_sdh_clk_register(core->name, base + core->offset,

					   __clk_get_name(parent), notifiers);



	case CLK_TYPE_GEN3_SD:

		return cpg_sd_clk_register(core->name, base, core->offset,

					   __clk_get_name(parent), notifiers,

drivers/clk/renesas/rcar-gen3-cpg.h

+4 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ enum rcar_gen3_clk_types { 
	CLK_TYPE_GEN3_PLL2,

	CLK_TYPE_GEN3_PLL3,

	CLK_TYPE_GEN3_PLL4,

	CLK_TYPE_GEN3_SDH,

	CLK_TYPE_GEN3_SD,

	CLK_TYPE_GEN3_R,

	CLK_TYPE_GEN3_MDSEL,	/* Select parent/divider using mode pin */
@@ -32,6 +33,9 @@ enum rcar_gen3_clk_types { 
	CLK_TYPE_GEN3_SOC_BASE,

};



#define DEF_GEN3_SDH(_name, _id, _parent, _offset)	\

	DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)



#define DEF_GEN3_SD(_name, _id, _parent, _offset)	\

	DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)