Commit a2fbfd51 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.16-2021-12-15' of... 

Merge tag 'amd-drm-fixes-5.16-2021-12-15' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-5.16-2021-12-15:

amdgpu:
- Fix RLC register offset
- GMC fix
- Properly cache SMU FW version on Yellow Carp
- Fix missing callback on DCN3.1
- Reset DMCUB before HW init
- Fix for GMC powergating on PCO
- Fix a possible memory leak in GPU metrics table handling on RN

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211216035239.5787-1-alexander.deucher@amd.com
parents 78fed39a aa464957

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+2 −2
Original line number Diff line number Diff line
@@ -3070,7 +3070,7 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev) 
			      AMD_PG_SUPPORT_CP |

			      AMD_PG_SUPPORT_GDS |

			      AMD_PG_SUPPORT_RLC_SMU_HS)) {

		WREG32(mmRLC_JUMP_TABLE_RESTORE,

		WREG32_SOC15(GC, 0, mmRLC_JUMP_TABLE_RESTORE,

			     adev->gfx.rlc.cp_table_gpu_addr >> 8);

		gfx_v9_0_init_gfx_power_gating(adev);

	}

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+0 −1
Original line number Diff line number Diff line
@@ -162,7 +162,6 @@ static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) 
			    ENABLE_ADVANCED_DRIVER_MODEL, 1);

	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);

	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

			    MTYPE, MTYPE_UC);/* XXX for emulation. */

	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

+0 −1
Original line number Diff line number Diff line
@@ -196,7 +196,6 @@ static void gfxhub_v2_0_init_tlb_regs(struct amdgpu_device *adev) 
			    ENABLE_ADVANCED_DRIVER_MODEL, 1);

	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);

	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

			    MTYPE, MTYPE_UC); /* UC, uncached */

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

+0 −1
Original line number Diff line number Diff line
@@ -197,7 +197,6 @@ static void gfxhub_v2_1_init_tlb_regs(struct amdgpu_device *adev) 
			    ENABLE_ADVANCED_DRIVER_MODEL, 1);

	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);

	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

			    MTYPE, MTYPE_UC); /* UC, uncached */

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+8 −0
Original line number Diff line number Diff line
@@ -1808,6 +1808,14 @@ static int gmc_v9_0_hw_fini(void *handle) 
		return 0;

	}



	/*

	 * Pair the operations did in gmc_v9_0_hw_init and thus maintain

	 * a correct cached state for GMC. Otherwise, the "gate" again

	 * operation on S3 resuming will fail due to wrong cached state.

	 */

	if (adev->mmhub.funcs->update_power_gating)

		adev->mmhub.funcs->update_power_gating(adev, false);



	amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);

	amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);