Commit a2e927b0 authored by Bjorn Andersson's avatar Bjorn Andersson Committed by Vinod Koul
Browse files

phy: qcom-qmp-combo: Add sc8280xp USB/DP combo phys 



The SC8280P has two copies of an USB/DP compbo PHY, add support for this
to the Qualcomm QMP PHY driver.

Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220810042303.3583194-5-bjorn.andersson@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent c0c7769c

drivers/phy/qualcomm/phy-qcom-qmp-combo.c

+339 −4
Original line number Diff line number Diff line
@@ -606,6 +606,160 @@ static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { 
	QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),

};



static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),

	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),

};



static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01),

};



static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a),

};



static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a),

};



static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05),

	QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f),

};



static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = {

	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),

	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),

	QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),

	QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),

	QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),

	QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),

	QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),

	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),

	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a),

	QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),

	QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),

	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),

	QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),

	QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),

	QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),

	QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),

};



/* list of regulators */

struct qmp_regulator_data {
@@ -646,6 +800,34 @@ static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { 
	{ 0x1f, 0xff, 0xff, 0xff }

};



static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = {

	{ 0x20, 0x2c, 0x35, 0x3b },

	{ 0x22, 0x2e, 0x36, 0xff },

	{ 0x22, 0x31, 0xff, 0xff },

	{ 0x24, 0xff, 0xff, 0xff }

};



static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = {

	{ 0x22, 0x32, 0x36, 0x3a },

	{ 0x29, 0x39, 0x3f, 0xff },

	{ 0x30, 0x3f, 0xff, 0xff },

	{ 0x3f, 0xff, 0xff, 0xff }

};



static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = {

	{ 0x20, 0x2d, 0x34, 0x3a },

	{ 0x20, 0x2e, 0x35, 0xff },

	{ 0x20, 0x2e, 0xff, 0xff },

	{ 0x24, 0xff, 0xff, 0xff }

};



static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = {

	{ 0x28, 0x2f, 0x36, 0x3f },

	{ 0x31, 0x3e, 0x3f, 0xff },

	{ 0x36, 0x3f, 0xff, 0xff },

	{ 0x3f, 0xff, 0xff, 0xff }

};



struct qmp_phy;



/* struct qmp_phy_cfg - per-PHY initialization config */
@@ -818,6 +1000,8 @@ static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy); 
static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);

static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);



static int qcom_qmp_v5_phy_configure_dp_phy(struct qmp_phy *qphy);



static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)

{

	u32 reg;
@@ -1060,6 +1244,83 @@ static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = { 
	.dp_cfg			= &sc8180x_dpphy_cfg,

};



static const struct qmp_phy_cfg sc8280xp_usb43dp_usb_cfg = {

	.type			= PHY_TYPE_USB3,

	.nlanes			= 1,



	.serdes_tbl		= sc8280xp_usb43dp_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl),

	.tx_tbl			= sc8280xp_usb43dp_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl),

	.rx_tbl			= sc8280xp_usb43dp_rx_tbl,

	.rx_tbl_num		= ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl),

	.pcs_tbl		= sc8280xp_usb43dp_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl),

	.clk_list		= qmp_v4_phy_clk_l,

	.num_clks		= ARRAY_SIZE(qmp_v4_phy_clk_l),

	.reset_list		= msm8996_usb3phy_reset_l,

	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),

	.vreg_list		= qmp_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),

	.regs			= qmp_v4_usb3phy_regs_layout,



	.start_ctrl		= SERDES_START | PCS_START,

	.pwrdn_ctrl		= SW_PWRDN,

	.phy_status		= PHYSTATUS,



	.has_pwrdn_delay	= true,

	.pwrdn_delay_min	= POWER_DOWN_DELAY_US_MIN,

	.pwrdn_delay_max	= POWER_DOWN_DELAY_US_MAX,



	.has_phy_dp_com_ctrl	= true,

	.is_dual_lane_phy	= true,

};



static const struct qmp_phy_cfg sc8280xp_usb43dp_dp_cfg = {

	.type			= PHY_TYPE_DP,

	.nlanes			= 1,



	.serdes_tbl		= qmp_v5_dp_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(qmp_v5_dp_serdes_tbl),

	.tx_tbl			= qmp_v5_5nm_dp_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl),



	.serdes_tbl_rbr		= qmp_v4_dp_serdes_tbl_rbr,

	.serdes_tbl_rbr_num	= ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),

	.serdes_tbl_hbr		= qmp_v4_dp_serdes_tbl_hbr,

	.serdes_tbl_hbr_num	= ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),

	.serdes_tbl_hbr2	= qmp_v4_dp_serdes_tbl_hbr2,

	.serdes_tbl_hbr2_num	= ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),

	.serdes_tbl_hbr3	= qmp_v4_dp_serdes_tbl_hbr3,

	.serdes_tbl_hbr3_num	= ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),



	.swing_hbr_rbr		= &qmp_dp_v5_voltage_swing_hbr_rbr,

	.pre_emphasis_hbr_rbr	= &qmp_dp_v5_pre_emphasis_hbr_rbr,

	.swing_hbr3_hbr2	= &qmp_dp_v5_voltage_swing_hbr3_hbr2,

	.pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,



	.clk_list		= qmp_v4_phy_clk_l,

	.num_clks		= ARRAY_SIZE(qmp_v4_phy_clk_l),

	.reset_list		= msm8996_usb3phy_reset_l,

	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),

	.vreg_list		= qmp_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),

	.regs			= qmp_v4_usb3phy_regs_layout,



	.has_phy_dp_com_ctrl	= true,

	.is_dual_lane_phy	= true,



	.dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,

	.configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,

	.configure_dp_phy = qcom_qmp_v5_phy_configure_dp_phy,

	.calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,

};



static const struct qmp_phy_combo_cfg sc8280xp_usb43dpphy_combo_cfg = {

	.usb_cfg		= &sc8280xp_usb43dp_usb_cfg,

	.dp_cfg			= &sc8280xp_usb43dp_dp_cfg,

};



static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {

	.type			= PHY_TYPE_USB3,

	.nlanes			= 1,
@@ -1479,18 +1740,16 @@ static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy) 
			QSERDES_V4_TX_TX_EMP_POST1_LVL);

}



static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)

static int qcom_qmp_v45_phy_configure_dp_phy(struct qmp_phy *qphy)

{

	const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;

	const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;

	u32 phy_vco_div, status;

	unsigned long pixel_freq;

	u32 bias0_en, drvr0_en, bias1_en, drvr1_en;

	bool reverse;



	writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);



	reverse = qcom_qmp_phy_combo_configure_dp_mode(qphy);

	qcom_qmp_phy_combo_configure_dp_mode(qphy);



	writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);

	writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
@@ -1568,6 +1827,21 @@ static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) 
			10000))

		return -ETIMEDOUT;



	return 0;

}



static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)

{

	const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;

	u32 bias0_en, drvr0_en, bias1_en, drvr1_en;

	bool reverse = false;

	u32 status;

	int ret;



	ret = qcom_qmp_v45_phy_configure_dp_phy(qphy);

	if (ret < 0)

		return ret;



	/*

	 * At least for 7nm DP PHY this has to be done after enabling link

	 * clock.
@@ -1618,6 +1892,63 @@ static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) 
	return 0;

}



static int qcom_qmp_v5_phy_configure_dp_phy(struct qmp_phy *qphy)

{

	const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;

	u32 bias0_en, drvr0_en, bias1_en, drvr1_en;

	bool reverse = false;

	u32 status;

	int ret;



	ret = qcom_qmp_v45_phy_configure_dp_phy(qphy);

	if (ret < 0)

		return ret;



	if (dp_opts->lanes == 1) {

		bias0_en = reverse ? 0x3e : 0x1a;

		drvr0_en = reverse ? 0x13 : 0x10;

		bias1_en = reverse ? 0x15 : 0x3e;

		drvr1_en = reverse ? 0x10 : 0x13;

	} else if (dp_opts->lanes == 2) {

		bias0_en = reverse ? 0x3f : 0x15;

		drvr0_en = 0x10;

		bias1_en = reverse ? 0x15 : 0x3f;

		drvr1_en = 0x10;

	} else {

		bias0_en = 0x3f;

		bias1_en = 0x3f;

		drvr0_en = 0x10;

		drvr1_en = 0x10;

	}



	writel(drvr0_en, qphy->tx + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN);

	writel(bias0_en, qphy->tx + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN);

	writel(drvr1_en, qphy->tx2 + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN);

	writel(bias1_en, qphy->tx2 + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN);



	writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);

	udelay(2000);

	writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);



	if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,

			status,

			((status & BIT(1)) > 0),

			500,

			10000))

		return -ETIMEDOUT;



	writel(0x0a, qphy->tx + QSERDES_V5_5NM_TX_TX_POL_INV);

	writel(0x0a, qphy->tx2 + QSERDES_V5_5NM_TX_TX_POL_INV);



	writel(0x27, qphy->tx + QSERDES_V5_5NM_TX_TX_DRV_LVL);

	writel(0x27, qphy->tx2 + QSERDES_V5_5NM_TX_TX_DRV_LVL);



	writel(0x20, qphy->tx + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL);

	writel(0x20, qphy->tx2 + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL);



	return 0;

}



/*

 * We need to calibrate the aux setting here as many times

 * as the caller tries
@@ -2512,6 +2843,10 @@ static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { 
		.compatible = "qcom,sc8180x-qmp-usb3-dp-phy",

		.data = &sc8180x_usb3dpphy_cfg,

	},

	{

		.compatible = "qcom,sc8280xp-qmp-usb43dp-phy",

		.data = &sc8280xp_usb43dpphy_combo_cfg,

	},

	{ }

};

MODULE_DEVICE_TABLE(of, qcom_qmp_combo_phy_of_match_table);

drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H		0x194

#define QPHY_V5_PCS_RATE_SLEW_CNTRL1			0x198

#define QPHY_V5_PCS_CDR_RESET_TIME			0x1b0

#define QPHY_V5_PCS_RX_CONFIG				0x1b0

#define QPHY_V5_PCS_ALIGN_DETECT_CONFIG1		0x1c0

#define QPHY_V5_PCS_ALIGN_DETECT_CONFIG2		0x1c4

#define QPHY_V5_PCS_PCS_TX_RX_CONFIG			0x1d0

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_5nm.h

0 → 100644
+333 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/phy/qualcomm/phy-qcom-qmp.h

+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
#include "phy-qcom-qmp-qserdes-com-v5.h"

#include "phy-qcom-qmp-qserdes-txrx-v5.h"

#include "phy-qcom-qmp-qserdes-txrx-v5_20.h"

#include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h"



#include "phy-qcom-qmp-qserdes-pll.h"