Commit a2e4b5ad authored by Michael Walle's avatar Michael Walle Committed by Jakub Kicinski
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dt-bindings: net: mscc-miim: add lan966x compatible 



The MDIO controller has support to release the internal PHYs from reset
by specifying a second memory resource. This is different between the
currently supported SparX-5 and the LAN966x. Add a new compatible to
distinguish between these two.

Signed-off-by: default avatarMichael Walle <michael@walle.cc>
Acked-by: default avatarHoratiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent c050f5e9

Documentation/devicetree/bindings/net/mscc-miim.txt

+1 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ Microsemi MII Management Controller (MIIM) / MDIO 
=================================================



Properties:

- compatible: must be "mscc,ocelot-miim"

- compatible: must be "mscc,ocelot-miim" or "microchip,lan966x-miim"

- reg: The base address of the MDIO bus controller register bank. Optionally, a

  second register bank can be defined if there is an associated reset register

  for internal PHYs