Commit a2a04b51 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-misc-fixes-2023-02-16' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixes 



Multiple fixes in vc4 to address issues with YUV planes, HDMI and CRTC;
an invalid page access fix for fbdev, mark dynamic debug as broken, a
double free and refcounting fix for vmwgfx.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20230216091905.i5wswy4dd74x4br5@houat
parents caa068c9 a950b989

drivers/gpu/drm/Kconfig

+2 −1
Original line number Diff line number Diff line
@@ -53,7 +53,8 @@ config DRM_DEBUG_MM 


config DRM_USE_DYNAMIC_DEBUG

	bool "use dynamic debug to implement drm.debug"

	default y

	default n

	depends on BROKEN

	depends on DRM

	depends on DYNAMIC_DEBUG || DYNAMIC_DEBUG_CORE

	depends on JUMP_LABEL

drivers/gpu/drm/ast/ast_mode.c

+2 −2
Original line number Diff line number Diff line
@@ -714,7 +714,7 @@ static int ast_primary_plane_init(struct ast_private *ast) 
	struct ast_plane *ast_primary_plane = &ast->primary_plane;

	struct drm_plane *primary_plane = &ast_primary_plane->base;

	void __iomem *vaddr = ast->vram;

	u64 offset = ast->vram_base;

	u64 offset = 0; /* with shmem, the primary plane is always at offset 0 */

	unsigned long cursor_size = roundup(AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE, PAGE_SIZE);

	unsigned long size = ast->vram_fb_available - cursor_size;

	int ret;
@@ -972,7 +972,7 @@ static int ast_cursor_plane_init(struct ast_private *ast) 
		return -ENOMEM;



	vaddr = ast->vram + ast->vram_fb_available - size;

	offset = ast->vram_base + ast->vram_fb_available - size;

	offset = ast->vram_fb_available - size;



	ret = ast_plane_init(dev, ast_cursor_plane, vaddr, offset, size,

			     0x01, &ast_cursor_plane_funcs,

drivers/gpu/drm/vc4/vc4_crtc.c

+1 −1
Original line number Diff line number Diff line
@@ -711,7 +711,7 @@ static int vc4_crtc_atomic_check(struct drm_crtc *crtc, 
		struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);



		if (vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0) {

			vc4_state->hvs_load = max(mode->clock * mode->hdisplay / mode->htotal + 1000,

			vc4_state->hvs_load = max(mode->clock * mode->hdisplay / mode->htotal + 8000,

						  mode->clock * 9 / 10) * 1000;

		} else {

			vc4_state->hvs_load = mode->clock * 1000;

drivers/gpu/drm/vc4/vc4_hdmi.c

+9 −9
Original line number Diff line number Diff line
@@ -97,6 +97,10 @@ 
#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT	8

#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK	VC4_MASK(15, 8)



#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK	VC4_MASK(7, 0)

#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE	BIT(0)

#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE	BIT(4)



# define VC4_HD_M_SW_RST			BIT(2)

# define VC4_HD_M_ENABLE			BIT(0)
@@ -1306,7 +1310,6 @@ static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 
					VC4_HDMI_VERTB_VBP));

	unsigned long flags;

	unsigned char gcp;

	bool gcp_en;

	u32 reg;

	int idx;
@@ -1341,16 +1344,13 @@ static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 
	switch (vc4_state->output_bpc) {

	case 12:

		gcp = 6;

		gcp_en = true;

		break;

	case 10:

		gcp = 5;

		gcp_en = true;

		break;

	case 8:

	default:

		gcp = 4;

		gcp_en = false;

		gcp = 0;

		break;

	}
@@ -1359,8 +1359,7 @@ static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 
	 * doesn't signal in GCP.

	 */

	if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {

		gcp = 4;

		gcp_en = false;

		gcp = 0;

	}



	reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
@@ -1373,11 +1372,12 @@ static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 
	reg = HDMI_READ(HDMI_GCP_WORD_1);

	reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;

	reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);

	reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK;

	reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE;

	HDMI_WRITE(HDMI_GCP_WORD_1, reg);



	reg = HDMI_READ(HDMI_GCP_CONFIG);

	reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;

	reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;

	reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE;

	HDMI_WRITE(HDMI_GCP_CONFIG, reg);



	reg = HDMI_READ(HDMI_MISC_CONTROL);

drivers/gpu/drm/vc4/vc4_plane.c

+4 −2
Original line number Diff line number Diff line
@@ -340,7 +340,7 @@ static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state) 
{

	struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);

	struct drm_framebuffer *fb = state->fb;

	struct drm_gem_dma_object *bo = drm_fb_dma_get_gem_obj(fb, 0);

	struct drm_gem_dma_object *bo;

	int num_planes = fb->format->num_planes;

	struct drm_crtc_state *crtc_state;

	u32 h_subsample = fb->format->hsub;
@@ -359,8 +359,10 @@ static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state) 
	if (ret)

		return ret;



	for (i = 0; i < num_planes; i++)

	for (i = 0; i < num_planes; i++) {

		bo = drm_fb_dma_get_gem_obj(fb, i);

		vc4_state->offsets[i] = bo->dma_addr + fb->offsets[i];

	}



	/*

	 * We don't support subpixel source positioning for scaling,