Commit a29ae860 authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Jerome Brunet
Browse files

clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers 



Not all u-boot versions initialize the HHI_GP_PLL_CNTL[2-5] registers.
In that case all HHI_GPLL_PLL_CNTL[1-5] registers are 0x0 and when
booting Linux the PLL fails to lock.
The initialization sequence from u-boot is:
- put the PLL into reset
- write 0x59C88000 to HHI_GP_PLL_CNTL2
- write 0xCA463823 to HHI_GP_PLL_CNTL3
- write 0x0286A027 to HHI_GP_PLL_CNTL4
- write 0x00003000 to HHI_GP_PLL_CNTL5
- set M, N, OD and the enable bit
- take the PLL out of reset
- check if it has locked
- disable the PLL

In Linux we already initialize M, N, OD, the enable and the reset bits.
Also the HHI_GP_PLL_CNTL[2-5] registers with these magic values (the
exact meaning is unknown) so the PLL can lock when the vendor u-boot did
not initialize these registers yet.

Fixes: b882964b ("clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2")
Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200501215717.735393-1-martin.blumenstingl@googlemail.com
parent 16afd70a

drivers/clk/meson/meson8b.c

+9 −0
Original line number Diff line number Diff line
@@ -1918,6 +1918,13 @@ static struct clk_regmap meson8b_mali = { 
	},

};



static const struct reg_sequence meson8m2_gp_pll_init_regs[] = {

	{ .reg = HHI_GP_PLL_CNTL2,	.def = 0x59c88000 },

	{ .reg = HHI_GP_PLL_CNTL3,	.def = 0xca463823 },

	{ .reg = HHI_GP_PLL_CNTL4,	.def = 0x0286a027 },

	{ .reg = HHI_GP_PLL_CNTL5,	.def = 0x00003000 },

};



static const struct pll_params_table meson8m2_gp_pll_params_table[] = {

	PLL_PARAMS(182, 3),

	{ /* sentinel */ },
@@ -1951,6 +1958,8 @@ static struct clk_regmap meson8m2_gp_pll_dco = { 
			.width   = 1,

		},

		.table = meson8m2_gp_pll_params_table,

		.init_regs = meson8m2_gp_pll_init_regs,

		.init_count = ARRAY_SIZE(meson8m2_gp_pll_init_regs),

	},

	.hw.init = &(struct clk_init_data){

		.name = "gp_pll_dco",

drivers/clk/meson/meson8b.h

+4 −0
Original line number Diff line number Diff line
@@ -20,6 +20,10 @@ 
 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf

 */

#define HHI_GP_PLL_CNTL			0x40  /* 0x10 offset in data sheet */

#define HHI_GP_PLL_CNTL2		0x44  /* 0x11 offset in data sheet */

#define HHI_GP_PLL_CNTL3		0x48  /* 0x12 offset in data sheet */

#define HHI_GP_PLL_CNTL4		0x4C  /* 0x13 offset in data sheet */

#define HHI_GP_PLL_CNTL5		0x50  /* 0x14 offset in data sheet */

#define HHI_VIID_CLK_DIV		0x128 /* 0x4a offset in data sheet */

#define HHI_VIID_CLK_CNTL		0x12c /* 0x4b offset in data sheet */

#define HHI_GCLK_MPEG0			0x140 /* 0x50 offset in data sheet */