Commit a283ea1b authored by Yevgeny Kliteynik's avatar Yevgeny Kliteynik Committed by Saeed Mahameed
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net/mlx5: DR, Avoid unnecessary csum recalculation on supporting devices 



If as part of the actions the TTL of the packet is modified, the packet's
checksum needs to be recalculated. Connect-X6DX can handle this csum
recalculation natively. Older devices require this additional recalculation.

Signed-off-by: default avatarYevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: default avatarAlex Vesker <valex@nvidia.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
parent 902c0245

drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c

+5 −4
Original line number Diff line number Diff line
@@ -447,7 +447,8 @@ int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher, 
		case DR_ACTION_TYP_MODIFY_HDR:

			attr.modify_index = action->rewrite.index;

			attr.modify_actions = action->rewrite.num_of_actions;

			recalc_cs_required = action->rewrite.modify_ttl;

			recalc_cs_required = action->rewrite.modify_ttl &&

					     !mlx5dr_ste_supp_ttl_cs_recalc(&dmn->info.caps);

			break;

		case DR_ACTION_TYP_L2_TO_TNL_L2:

		case DR_ACTION_TYP_L2_TO_TNL_L3:
@@ -501,9 +502,9 @@ int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher, 
	*new_hw_ste_arr_sz = nic_matcher->num_of_builders;

	last_ste = ste_arr + DR_STE_SIZE * (nic_matcher->num_of_builders - 1);



	/* Due to a HW bug, modifying TTL on RX flows will cause an incorrect

	 * checksum calculation. In this case we will use a FW table to

	 * recalculate.

	/* Due to a HW bug in some devices, modifying TTL on RX flows will

	 * cause an incorrect checksum calculation. In this case we will

	 * use a FW table to recalculate.

	 */

	if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB &&

	    rx_rule && recalc_cs_required && dest_action) {

drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c

+5 −0
Original line number Diff line number Diff line
@@ -18,6 +18,11 @@ static u32 dr_ste_crc32_calc(const void *input_data, size_t length) 
	return (__force u32)htonl(crc);

}



bool mlx5dr_ste_supp_ttl_cs_recalc(struct mlx5dr_cmd_caps *caps)

{

	return caps->sw_format_ver > MLX5_STEERING_FORMAT_CONNECTX_5;

}



u32 mlx5dr_ste_calc_hash_index(u8 *hw_ste_p, struct mlx5dr_ste_htbl *htbl)

{

	struct dr_hw_ste_format *hw_ste = (struct dr_hw_ste_format *)hw_ste_p;

drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h

+2 −0
Original line number Diff line number Diff line
@@ -1211,6 +1211,8 @@ int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev, 
		       u32 group_id,

		       struct mlx5dr_cmd_fte_info *fte);



bool mlx5dr_ste_supp_ttl_cs_recalc(struct mlx5dr_cmd_caps *caps);



struct mlx5dr_fw_recalc_cs_ft {

	u64 rx_icm_addr;

	u32 table_id;