Merge branches 'for-next/misc', 'for-next/kselftest', 'for-next/xntable',...

				   state is kept private from the host.

				   Not valid if the kernel is running in EL2.

			Defaults to VHE/nVHE based on hardware support and

			the value of CONFIG_ARM64_VHE.

			Defaults to VHE/nVHE based on hardware support.

	kvm-arm.vgic_v3_group0_trap=

			[KVM,ARM] Trap guest accesses to GICv3 group-0

  $# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5

  $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5

For HiSilicon uncore PMU v2 whose identifier is 0x30, the topology is the same

as PMU v1, but some new functions are added to the hardware.

(a) L3C PMU supports filtering by core/thread within the cluster which can be

specified as a bitmap::

  $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5

This will only count the operations from core/thread 0 and 1 in this cluster.

(b) Tracetag allow the user to chose to count only read, write or atomic

operations via the tt_req parameeter in perf. The default value counts all

operations. tt_req is 3bits, 3'b100 represents read operations, 3'b101

represents write operations, 3'b110 represents atomic store operations and

3'b111 represents atomic non-store operations, other values are reserved::

  $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5

This will only count the read operations in this cluster.

(c) Datasrc allows the user to check where the data comes from. It is 5 bits.

Some important codes are as follows:

5'b00001: comes from L3C in this die;

5'b01000: comes from L3C in the cross-die;

5'b01001: comes from L3C which is in another socket;

5'b01110: comes from the local DDR;

5'b01111: comes from the cross-die DDR;

5'b10000: comes from cross-socket DDR;

etc, it is mainly helpful to find that the data source is nearest from the CPU

cores. If datasrc_cfg is used in the multi-chips, the datasrc_skt shall be

configured in perf command::

  $# perf stat -a -e hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xE/,

  hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xF/ sleep 5

(d)Some HiSilicon SoCs encapsulate multiple CPU and IO dies. Each CPU die

contains several Compute Clusters (CCLs). The I/O dies are called Super I/O

clusters (SICL) containing multiple I/O clusters (ICLs). Each CCL/ICL in the

SoC has a unique ID. Each ID is 11bits, include a 6-bit SCCL-ID and 5-bit

CCL/ICL-ID. For I/O die, the ICL-ID is followed by:

5'b00000: I/O_MGMT_ICL;

5'b00001: Network_ICL;

5'b00011: HAC_ICL;

5'b10000: PCIe_ICL;

Users could configure IDs to count data come from specific CCL/ICL, by setting

srcid_cmd & srcid_msk, and data desitined for specific CCL/ICL by setting

tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will not

check the bit when matching against the srcid_cmd/tgtid_cmd.

If all of these options are disabled, it can works by the default value that

doesn't distinguish the filter condition and ID information and will return

the total counter values in the PMU counters.

The current driver does not support sampling. So "perf record" is unsupported.

Also attach to a task is unsupported as the events are all uncore.

- System registers

  All writable architected system registers at the exception level where

  the kernel image will be entered must be initialised by software at a

  higher exception level to prevent execution in an UNKNOWN state.

  All writable architected system registers at or below the exception

  level where the kernel image will be entered must be initialised by

  software at a higher exception level to prevent execution in an UNKNOWN

  state.

  - SCR_EL3.FIQ must have the same value across all CPUs the kernel is

    executing on.

      having 0b1 set for the corresponding bit for each of the auxiliary

      counters present.

  For CPUs with the Fine Grained Traps (FEAT_FGT) extension present:

  - If EL3 is present and the kernel is entered at EL2:

    - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.

The requirements described above for CPU mode, caches, MMUs, architected

timers, coherency and system registers apply to all CPUs.  All CPUs must

enter the kernel in the same exception level.

	select GENERIC_FIND_FIRST_BIT

	select GENERIC_IDLE_POLL_SETUP

	select GENERIC_IRQ_IPI

	select GENERIC_IRQ_MULTI_HANDLER

	select GENERIC_IRQ_PROBE

	select GENERIC_IRQ_SHOW

	select GENERIC_IRQ_SHOW_LEVEL

	select HAVE_ARCH_JUMP_LABEL

	select HAVE_ARCH_JUMP_LABEL_RELATIVE

	select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)

	select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN

	select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN

	select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)

	select HAVE_ARCH_KFENCE

	select IOMMU_DMA if IOMMU_SUPPORT

	select IRQ_DOMAIN

	select IRQ_FORCED_THREADING

	select KASAN_VMALLOC if KASAN_GENERIC

	select MODULES_USE_ELF_RELA

	select NEED_DMA_MAP_STATE

	select NEED_SG_DMA_LENGTH

config ARCH_HAS_CACHE_LINE_SIZE

	def_bool y

config ARCH_HAS_FILTER_PGPROT

	def_bool y

config ARCH_ENABLE_SPLIT_PMD_PTLOCK

	def_bool y if PGTABLE_LEVELS > 2

	  built with binutils >= 2.25 in order for the new instructions

	  to be used.

config ARM64_VHE

	bool "Enable support for Virtualization Host Extensions (VHE)"

	default y

	help

	  Virtualization Host Extensions (VHE) allow the kernel to run

	  directly at EL2 (instead of EL1) on processors that support

	  it. This leads to better performance for KVM, as they reduce

	  the cost of the world switch.

	  Selecting this option allows the VHE feature to be detected

	  at runtime, and does not affect processors that do not

	  implement this feature.

endmenu

menu "ARMv8.2 architectural features"

endmenu

menu "ARMv8.7 architectural features"

config ARM64_EPAN

	bool "Enable support for Enhanced Privileged Access Never (EPAN)"

	default y

	depends on ARM64_PAN

	help

	 Enhanced Privileged Access Never (EPAN) allows Privileged

	 Access Never to be used with Execute-only mappings.

	 The feature is detected at runtime, and will remain disabled

	 if the cpu does not implement the feature.

endmenu

config ARM64_SVE

	bool "ARM Scalable Vector Extension support"

	default y

	depends on !KVM || ARM64_VHE

	help

	  The Scalable Vector Extension (SVE) is an extension to the AArch64

	  execution state which complements and extends the SIMD functionality

	  booting the kernel.  If unsure and you are not observing these

	  symptoms, you should assume that it is safe to say Y.

	  CPUs that support SVE are architecturally required to support the

	  Virtualization Host Extensions (VHE), so the kernel makes no

	  provision for supporting SVE alongside KVM without VHE enabled.

	  Thus, you will need to enable CONFIG_ARM64_VHE if you want to support

	  KVM in the same kernel image.

config ARM64_MODULE_PLTS

	bool "Use PLTs to allow module memory to spill over into vmalloc area"

	depends on MODULES

	cbz		w5, .Lmacout

	encrypt_block	v0, w2, x1, x7, w8

	st1		{v0.16b}, [x4]			/* return dg */

	cond_yield	.Lmacout, x7

	cond_yield	.Lmacout, x7, x8

	b		.Lmacloop4x

.Lmac1x:

	add		w3, w3, #4