Loading drivers/iommu/intel-iommu.c +39 −0 Original line number Diff line number Diff line Loading @@ -307,6 +307,14 @@ static int hw_pass_through = 1; */ #define DOMAIN_FLAG_LOSE_CHILDREN BIT(1) /* * When VT-d works in the scalable mode, it allows DMA translation to * happen through either first level or second level page table. This * bit marks that the DMA translation for the domain goes through the * first level page table, otherwise, it goes through the second level. */ #define DOMAIN_FLAG_USE_FIRST_LEVEL BIT(2) #define for_each_domain_iommu(idx, domain) \ for (idx = 0; idx < g_num_of_iommus; idx++) \ if (domain->iommu_refcnt[idx]) Loading Loading @@ -1714,6 +1722,35 @@ static void free_dmar_iommu(struct intel_iommu *iommu) #endif } /* * Check and return whether first level is used by default for * DMA translation. Currently, we make it off by setting * first_level_support = 0, and will change it to -1 after all * map/unmap paths support first level page table. */ static bool first_level_by_default(void) { struct dmar_drhd_unit *drhd; struct intel_iommu *iommu; static int first_level_support = 0; if (likely(first_level_support != -1)) return first_level_support; first_level_support = 1; rcu_read_lock(); for_each_active_iommu(iommu, drhd) { if (!sm_supported(iommu) || !ecap_flts(iommu->ecap)) { first_level_support = 0; break; } } rcu_read_unlock(); return first_level_support; } static struct dmar_domain *alloc_domain(int flags) { struct dmar_domain *domain; Loading @@ -1725,6 +1762,8 @@ static struct dmar_domain *alloc_domain(int flags) memset(domain, 0, sizeof(*domain)); domain->nid = NUMA_NO_NODE; domain->flags = flags; if (first_level_by_default()) domain->flags |= DOMAIN_FLAG_USE_FIRST_LEVEL; domain->has_iotlb_device = false; INIT_LIST_HEAD(&domain->devices); Loading Loading
drivers/iommu/intel-iommu.c +39 −0 Original line number Diff line number Diff line Loading @@ -307,6 +307,14 @@ static int hw_pass_through = 1; */ #define DOMAIN_FLAG_LOSE_CHILDREN BIT(1) /* * When VT-d works in the scalable mode, it allows DMA translation to * happen through either first level or second level page table. This * bit marks that the DMA translation for the domain goes through the * first level page table, otherwise, it goes through the second level. */ #define DOMAIN_FLAG_USE_FIRST_LEVEL BIT(2) #define for_each_domain_iommu(idx, domain) \ for (idx = 0; idx < g_num_of_iommus; idx++) \ if (domain->iommu_refcnt[idx]) Loading Loading @@ -1714,6 +1722,35 @@ static void free_dmar_iommu(struct intel_iommu *iommu) #endif } /* * Check and return whether first level is used by default for * DMA translation. Currently, we make it off by setting * first_level_support = 0, and will change it to -1 after all * map/unmap paths support first level page table. */ static bool first_level_by_default(void) { struct dmar_drhd_unit *drhd; struct intel_iommu *iommu; static int first_level_support = 0; if (likely(first_level_support != -1)) return first_level_support; first_level_support = 1; rcu_read_lock(); for_each_active_iommu(iommu, drhd) { if (!sm_supported(iommu) || !ecap_flts(iommu->ecap)) { first_level_support = 0; break; } } rcu_read_unlock(); return first_level_support; } static struct dmar_domain *alloc_domain(int flags) { struct dmar_domain *domain; Loading @@ -1725,6 +1762,8 @@ static struct dmar_domain *alloc_domain(int flags) memset(domain, 0, sizeof(*domain)); domain->nid = NUMA_NO_NODE; domain->flags = flags; if (first_level_by_default()) domain->flags |= DOMAIN_FLAG_USE_FIRST_LEVEL; domain->has_iotlb_device = false; INIT_LIST_HEAD(&domain->devices); Loading