Commit a190f8dc authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: header cleanup 



No function change, just move a bunch of definitions from amdgpu.h into
separate header files.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Acked-by: default avatarAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8c7442f0

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+0 −95
Original line number Diff line number Diff line
@@ -60,7 +60,6 @@ 
#include <drm/amdgpu_drm.h>

#include <drm/drm_gem.h>

#include <drm/drm_ioctl.h>

#include <drm/gpu_scheduler.h>



#include <kgd_kfd_interface.h>

#include "dm_pp_interface.h"
@@ -277,9 +276,6 @@ extern int amdgpu_vcnfw_log; 
#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)



struct amdgpu_device;

struct amdgpu_ib;

struct amdgpu_cs_parser;

struct amdgpu_job;

struct amdgpu_irq_src;

struct amdgpu_fpriv;

struct amdgpu_bo_va_mapping;
@@ -467,20 +463,6 @@ struct amdgpu_flip_work { 
};





/*

 * CP & rings.

 */



struct amdgpu_ib {

	struct amdgpu_sa_bo		*sa_bo;

	uint32_t			length_dw;

	uint64_t			gpu_addr;

	uint32_t			*ptr;

	uint32_t			flags;

};



extern const struct drm_sched_backend_ops amdgpu_sched_ops;



/*

 * file private structure

 */
@@ -496,79 +478,6 @@ struct amdgpu_fpriv { 


int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);



int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,

		  unsigned size,

		  enum amdgpu_ib_pool_type pool,

		  struct amdgpu_ib *ib);

void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,

		    struct dma_fence *f);

int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,

		       struct amdgpu_ib *ibs, struct amdgpu_job *job,

		       struct dma_fence **f);

int amdgpu_ib_pool_init(struct amdgpu_device *adev);

void amdgpu_ib_pool_fini(struct amdgpu_device *adev);

int amdgpu_ib_ring_tests(struct amdgpu_device *adev);



/*

 * CS.

 */

struct amdgpu_cs_chunk {

	uint32_t		chunk_id;

	uint32_t		length_dw;

	void			*kdata;

};



struct amdgpu_cs_post_dep {

	struct drm_syncobj *syncobj;

	struct dma_fence_chain *chain;

	u64 point;

};



struct amdgpu_cs_parser {

	struct amdgpu_device	*adev;

	struct drm_file		*filp;

	struct amdgpu_ctx	*ctx;



	/* chunks */

	unsigned		nchunks;

	struct amdgpu_cs_chunk	*chunks;



	/* scheduler job object */

	struct amdgpu_job	*job;

	struct drm_sched_entity	*entity;



	/* buffer objects */

	struct ww_acquire_ctx		ticket;

	struct amdgpu_bo_list		*bo_list;

	struct amdgpu_mn		*mn;

	struct amdgpu_bo_list_entry	vm_pd;

	struct list_head		validated;

	struct dma_fence		*fence;

	uint64_t			bytes_moved_threshold;

	uint64_t			bytes_moved_vis_threshold;

	uint64_t			bytes_moved;

	uint64_t			bytes_moved_vis;



	/* user fence */

	struct amdgpu_bo_list_entry	uf_entry;



	unsigned			num_post_deps;

	struct amdgpu_cs_post_dep	*post_deps;

};



static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,

				      uint32_t ib_idx, int idx)

{

	return p->job->ibs[ib_idx].ptr[idx];

}



static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,

				       uint32_t ib_idx, int idx,

				       uint32_t value)

{

	p->job->ibs[ib_idx].ptr[idx] = value;

}



/*

 * Writeback

 */
@@ -1439,10 +1348,6 @@ static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { retu 
static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }

#endif



int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,

			   uint64_t addr, struct amdgpu_bo **bo,

			   struct amdgpu_bo_va_mapping **mapping);



#if defined(CONFIG_DRM_AMD_DC)

int amdgpu_dm_display_resume(struct amdgpu_device *adev );

#else

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+1 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ 


#include <drm/amdgpu_drm.h>

#include <drm/drm_syncobj.h>

#include "amdgpu_cs.h"

#include "amdgpu.h"

#include "amdgpu_trace.h"

#include "amdgpu_gmc.h"

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.h

0 → 100644
+93 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2022 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#ifndef __AMDGPU_CS_H__

#define __AMDGPU_CS_H__



#include "amdgpu_job.h"

#include "amdgpu_bo_list.h"

#include "amdgpu_ring.h"



struct amdgpu_bo_va_mapping;



struct amdgpu_cs_chunk {

	uint32_t		chunk_id;

	uint32_t		length_dw;

	void			*kdata;

};



struct amdgpu_cs_post_dep {

	struct drm_syncobj *syncobj;

	struct dma_fence_chain *chain;

	u64 point;

};



struct amdgpu_cs_parser {

	struct amdgpu_device	*adev;

	struct drm_file		*filp;

	struct amdgpu_ctx	*ctx;



	/* chunks */

	unsigned		nchunks;

	struct amdgpu_cs_chunk	*chunks;



	/* scheduler job object */

	struct amdgpu_job	*job;

	struct drm_sched_entity	*entity;



	/* buffer objects */

	struct ww_acquire_ctx		ticket;

	struct amdgpu_bo_list		*bo_list;

	struct amdgpu_mn		*mn;

	struct amdgpu_bo_list_entry	vm_pd;

	struct list_head		validated;

	struct dma_fence		*fence;

	uint64_t			bytes_moved_threshold;

	uint64_t			bytes_moved_vis_threshold;

	uint64_t			bytes_moved;

	uint64_t			bytes_moved_vis;



	/* user fence */

	struct amdgpu_bo_list_entry	uf_entry;



	unsigned			num_post_deps;

	struct amdgpu_cs_post_dep	*post_deps;

};



static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,

				      uint32_t ib_idx, int idx)

{

	return p->job->ibs[ib_idx].ptr[idx];

}



static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,

				       uint32_t ib_idx, int idx,

				       uint32_t value)

{

	p->job->ibs[ib_idx].ptr[idx] = value;

}



int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,

			   uint64_t addr, struct amdgpu_bo **bo,

			   struct amdgpu_bo_va_mapping **mapping);



#endif

drivers/gpu/drm/amd/amdgpu/amdgpu_job.h

+3 −0
Original line number Diff line number Diff line
@@ -23,6 +23,9 @@ 
#ifndef __AMDGPU_JOB_H__

#define __AMDGPU_JOB_H__



#include <drm/gpu_scheduler.h>

#include "amdgpu_sync.h"



/* bit set means command submit involves a preamble IB */

#define AMDGPU_PREAMBLE_IB_PRESENT          (1 << 0)

/* bit set means preamble IB is first presented in belonging context */

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h

+30 −5
Original line number Diff line number Diff line
@@ -28,6 +28,13 @@ 
#include <drm/gpu_scheduler.h>

#include <drm/drm_print.h>



struct amdgpu_device;

struct amdgpu_ring;

struct amdgpu_ib;

struct amdgpu_cs_parser;

struct amdgpu_job;

struct amdgpu_vm;



/* max number of rings */

#define AMDGPU_MAX_RINGS		28

#define AMDGPU_MAX_HWIP_RINGS		8
@@ -82,11 +89,13 @@ enum amdgpu_ib_pool_type { 
	AMDGPU_IB_POOL_MAX

};



struct amdgpu_device;

struct amdgpu_ring;

struct amdgpu_ib;

struct amdgpu_cs_parser;

struct amdgpu_job;

struct amdgpu_ib {

	struct amdgpu_sa_bo		*sa_bo;

	uint32_t			length_dw;

	uint64_t			gpu_addr;

	uint32_t			*ptr;

	uint32_t			flags;

};



struct amdgpu_sched {

	u32				num_scheds;
@@ -111,6 +120,8 @@ struct amdgpu_fence_driver { 
	struct dma_fence		**fences;

};



extern const struct drm_sched_backend_ops amdgpu_sched_ops;



void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);

void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
@@ -352,4 +363,18 @@ int amdgpu_ring_test_helper(struct amdgpu_ring *ring); 


void amdgpu_debugfs_ring_init(struct amdgpu_device *adev,

			      struct amdgpu_ring *ring);



int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,

		  unsigned size,

		  enum amdgpu_ib_pool_type pool,

		  struct amdgpu_ib *ib);

void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,

		    struct dma_fence *f);

int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,

		       struct amdgpu_ib *ibs, struct amdgpu_job *job,

		       struct dma_fence **f);

int amdgpu_ib_pool_init(struct amdgpu_device *adev);

void amdgpu_ib_pool_fini(struct amdgpu_device *adev);

int amdgpu_ib_ring_tests(struct amdgpu_device *adev);



#endif