Commit a1319260 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Mathieu Poirier
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arm64: KVM: Enable access to TRBE support for host 

For a nvhe host, the EL2 must allow the EL1&0 translation
regime for TraceBuffer (MDCR_EL2.E2TB == 0b11). This must
be saved/restored over a trip to the guest. Also, before
entering the guest, we must flush any trace data if the
TRBE was enabled. And we must prohibit the generation
of trace while we are in EL1 by clearing the TRFCR_EL1.

For vhe, the EL2 must prevent the EL1 access to the Trace
Buffer.

The MDCR_EL2 bit definitions for TRBE are available here :

  https://developer.arm.com/documentation/ddi0601/2020-12/AArch64-Registers/



Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210405164307.1720226-8-suzuki.poulose@arm.com


Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
parent d2602bb4

arch/arm64/include/asm/el2_setup.h

+13 −0
Original line number Diff line number Diff line
@@ -65,6 +65,19 @@ 
						// use EL1&0 translation.



.Lskip_spe_\@:

	/* Trace buffer */

	ubfx	x0, x1, #ID_AA64DFR0_TRBE_SHIFT, #4

	cbz	x0, .Lskip_trace_\@		// Skip if TraceBuffer is not present



	mrs_s	x0, SYS_TRBIDR_EL1

	and	x0, x0, TRBIDR_PROG

	cbnz	x0, .Lskip_trace_\@		// If TRBE is available at EL2



	mov	x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT)

	orr	x2, x2, x0			// allow the EL1&0 translation

						// to own it.



.Lskip_trace_\@:

	msr	mdcr_el2, x2			// Configure debug traps

.endm

arch/arm64/include/asm/kvm_arm.h

+2 −0
Original line number Diff line number Diff line
@@ -278,6 +278,8 @@ 
#define CPTR_EL2_DEFAULT	CPTR_EL2_RES1



/* Hyp Debug Configuration Register bits */

#define MDCR_EL2_E2TB_MASK	(UL(0x3))

#define MDCR_EL2_E2TB_SHIFT	(UL(24))

#define MDCR_EL2_TTRF		(1 << 19)

#define MDCR_EL2_TPMS		(1 << 14)

#define MDCR_EL2_E2PB_MASK	(UL(0x3))

arch/arm64/include/asm/kvm_host.h

+3 −0
Original line number Diff line number Diff line
@@ -315,6 +315,8 @@ struct kvm_vcpu_arch { 
		struct kvm_guest_debug_arch regs;

		/* Statistical profiling extension */

		u64 pmscr_el1;

		/* Self-hosted trace */

		u64 trfcr_el1;

	} host_debug_state;



	/* VGIC state */
@@ -401,6 +403,7 @@ struct kvm_vcpu_arch { 
#define KVM_ARM64_PENDING_EXCEPTION	(1 << 8) /* Exception pending */

#define KVM_ARM64_EXCEPT_MASK		(7 << 9) /* Target EL/MODE */

#define KVM_ARM64_DEBUG_STATE_SAVE_SPE	(1 << 12) /* Save SPE context if active  */

#define KVM_ARM64_DEBUG_STATE_SAVE_TRBE	(1 << 13) /* Save TRBE context if active  */



/*

 * When KVM_ARM64_PENDING_EXCEPTION is set, KVM_ARM64_EXCEPT_MASK can

arch/arm64/kernel/hyp-stub.S

+2 −1
Original line number Diff line number Diff line
@@ -115,9 +115,10 @@ SYM_CODE_START_LOCAL(mutate_to_vhe) 
	mrs_s	x0, SYS_VBAR_EL12

	msr	vbar_el1, x0



	// Use EL2 translations for SPE and disable access from EL1

	// Use EL2 translations for SPE & TRBE and disable access from EL1

	mrs	x0, mdcr_el2

	bic	x0, x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)

	bic	x0, x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT)

	msr	mdcr_el2, x0



	// Transfer the MM state from EL1 to EL2

arch/arm64/kvm/debug.c

+10 −4
Original line number Diff line number Diff line
@@ -89,7 +89,7 @@ void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu) 
 *  - Debug ROM Address (MDCR_EL2_TDRA)

 *  - OS related registers (MDCR_EL2_TDOSA)

 *  - Statistical profiler (MDCR_EL2_TPMS/MDCR_EL2_E2PB)

 *  - Self-hosted Trace Filter controls (MDCR_EL2_TTRF)

 *  - Self-hosted Trace (MDCR_EL2_TTRF/MDCR_EL2_E2TB)

 *

 * Additionally, KVM only traps guest accesses to the debug registers if

 * the guest is not actively using them (see the KVM_ARM64_DEBUG_DIRTY
@@ -107,8 +107,8 @@ void kvm_arm_setup_debug(struct kvm_vcpu *vcpu) 
	trace_kvm_arm_setup_debug(vcpu, vcpu->guest_debug);



	/*

	 * This also clears MDCR_EL2_E2PB_MASK to disable guest access

	 * to the profiling buffer.

	 * This also clears MDCR_EL2_E2PB_MASK and MDCR_EL2_E2TB_MASK

	 * to disable guest access to the profiling and trace buffers

	 */

	vcpu->arch.mdcr_el2 = __this_cpu_read(mdcr_el2) & MDCR_EL2_HPMN_MASK;

	vcpu->arch.mdcr_el2 |= (MDCR_EL2_TPM |
@@ -248,9 +248,15 @@ void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu) 
	if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_PMSVER_SHIFT) &&

	    !(read_sysreg_s(SYS_PMBIDR_EL1) & BIT(SYS_PMBIDR_EL1_P_SHIFT)))

		vcpu->arch.flags |= KVM_ARM64_DEBUG_STATE_SAVE_SPE;



	/* Check if we have TRBE implemented and available at the host */

	if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_TRBE_SHIFT) &&

	    !(read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_PROG))

		vcpu->arch.flags |= KVM_ARM64_DEBUG_STATE_SAVE_TRBE;

}



void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu)

{

	vcpu->arch.flags &= ~KVM_ARM64_DEBUG_STATE_SAVE_SPE;

	vcpu->arch.flags &= ~(KVM_ARM64_DEBUG_STATE_SAVE_SPE |

			      KVM_ARM64_DEBUG_STATE_SAVE_TRBE);

}