Commit a13144e2 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/gmch: split out soc/intel_gmch 



The GMCH related code is a bit too low level and out of place for the
high level i915_driver.c file. Split out to a separate file under
soc/. Rename the functions accordingly.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/980a5e08b397bc0dbccf93cd84798772233ce75c.1673958757.git.jani.nikula@intel.com
parent 9bd5de4a

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -63,6 +63,7 @@ i915-y += i915_driver.o \ 
# core peripheral code

i915-y += \

	soc/intel_dram.o \

	soc/intel_gmch.o \

	soc/intel_pch.o



# core library code

drivers/gpu/drm/i915/i915_driver.c

+5 −140
Original line number Diff line number Diff line
@@ -34,7 +34,6 @@ 
#include <linux/pci.h>

#include <linux/pm.h>

#include <linux/pm_runtime.h>

#include <linux/pnp.h>

#include <linux/slab.h>

#include <linux/string_helpers.h>

#include <linux/vga_switcheroo.h>
@@ -78,6 +77,7 @@ 
#include "pxp/intel_pxp_pm.h"



#include "soc/intel_dram.h"

#include "soc/intel_gmch.h"



#include "i915_file_private.h"

#include "i915_debugfs.h"
@@ -107,141 +107,6 @@ 


static const struct drm_driver i915_drm_driver;



static void i915_release_bridge_dev(struct drm_device *dev,

				    void *bridge)

{

	pci_dev_put(bridge);

}



static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)

{

	int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);



	dev_priv->gmch.pdev =

		pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));

	if (!dev_priv->gmch.pdev) {

		drm_err(&dev_priv->drm, "bridge device not found\n");

		return -EIO;

	}



	return drmm_add_action_or_reset(&dev_priv->drm, i915_release_bridge_dev,

					dev_priv->gmch.pdev);

}



/* Allocate space for the MCH regs if needed, return nonzero on error */

static int

intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)

{

	int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;

	u32 temp_lo, temp_hi = 0;

	u64 mchbar_addr;

	int ret;



	if (GRAPHICS_VER(dev_priv) >= 4)

		pci_read_config_dword(dev_priv->gmch.pdev, reg + 4, &temp_hi);

	pci_read_config_dword(dev_priv->gmch.pdev, reg, &temp_lo);

	mchbar_addr = ((u64)temp_hi << 32) | temp_lo;



	/* If ACPI doesn't have it, assume we need to allocate it ourselves */

#ifdef CONFIG_PNP

	if (mchbar_addr &&

	    pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))

		return 0;

#endif



	/* Get some space for it */

	dev_priv->gmch.mch_res.name = "i915 MCHBAR";

	dev_priv->gmch.mch_res.flags = IORESOURCE_MEM;

	ret = pci_bus_alloc_resource(dev_priv->gmch.pdev->bus,

				     &dev_priv->gmch.mch_res,

				     MCHBAR_SIZE, MCHBAR_SIZE,

				     PCIBIOS_MIN_MEM,

				     0, pcibios_align_resource,

				     dev_priv->gmch.pdev);

	if (ret) {

		drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);

		dev_priv->gmch.mch_res.start = 0;

		return ret;

	}



	if (GRAPHICS_VER(dev_priv) >= 4)

		pci_write_config_dword(dev_priv->gmch.pdev, reg + 4,

				       upper_32_bits(dev_priv->gmch.mch_res.start));



	pci_write_config_dword(dev_priv->gmch.pdev, reg,

			       lower_32_bits(dev_priv->gmch.mch_res.start));

	return 0;

}



/* Setup MCHBAR if possible, return true if we should disable it again */

static void

intel_setup_mchbar(struct drm_i915_private *dev_priv)

{

	int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;

	u32 temp;

	bool enabled;



	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))

		return;



	dev_priv->gmch.mchbar_need_disable = false;



	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {

		pci_read_config_dword(dev_priv->gmch.pdev, DEVEN, &temp);

		enabled = !!(temp & DEVEN_MCHBAR_EN);

	} else {

		pci_read_config_dword(dev_priv->gmch.pdev, mchbar_reg, &temp);

		enabled = temp & 1;

	}



	/* If it's already enabled, don't have to do anything */

	if (enabled)

		return;



	if (intel_alloc_mchbar_resource(dev_priv))

		return;



	dev_priv->gmch.mchbar_need_disable = true;



	/* Space is allocated or reserved, so enable it. */

	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {

		pci_write_config_dword(dev_priv->gmch.pdev, DEVEN,

				       temp | DEVEN_MCHBAR_EN);

	} else {

		pci_read_config_dword(dev_priv->gmch.pdev, mchbar_reg, &temp);

		pci_write_config_dword(dev_priv->gmch.pdev, mchbar_reg, temp | 1);

	}

}



static void

intel_teardown_mchbar(struct drm_i915_private *dev_priv)

{

	int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;



	if (dev_priv->gmch.mchbar_need_disable) {

		if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {

			u32 deven_val;



			pci_read_config_dword(dev_priv->gmch.pdev, DEVEN,

					      &deven_val);

			deven_val &= ~DEVEN_MCHBAR_EN;

			pci_write_config_dword(dev_priv->gmch.pdev, DEVEN,

					       deven_val);

		} else {

			u32 mchbar_val;



			pci_read_config_dword(dev_priv->gmch.pdev, mchbar_reg,

					      &mchbar_val);

			mchbar_val &= ~1;

			pci_write_config_dword(dev_priv->gmch.pdev, mchbar_reg,

					       mchbar_val);

		}

	}



	if (dev_priv->gmch.mch_res.start)

		release_resource(&dev_priv->gmch.mch_res);

}



static int i915_workqueues_init(struct drm_i915_private *dev_priv)

{

	/*
@@ -447,7 +312,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 
	if (i915_inject_probe_failure(dev_priv))

		return -ENODEV;



	ret = i915_get_bridge_dev(dev_priv);

	ret = intel_gmch_bridge_setup(dev_priv);

	if (ret < 0)

		return ret;
@@ -464,7 +329,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 
	}



	/* Try to make sure MCHBAR is enabled before poking at it */

	intel_setup_mchbar(dev_priv);

	intel_gmch_bar_setup(dev_priv);

	intel_device_info_runtime_init(dev_priv);



	for_each_gt(gt, dev_priv, i) {
@@ -479,7 +344,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 
	return 0;



err_uncore:

	intel_teardown_mchbar(dev_priv);

	intel_gmch_bar_teardown(dev_priv);



	return ret;

}
@@ -490,7 +355,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 
 */

static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)

{

	intel_teardown_mchbar(dev_priv);

	intel_gmch_bar_teardown(dev_priv);

}



/**

drivers/gpu/drm/i915/soc/intel_gmch.c

0 → 100644
+145 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: MIT

/*

 * Copyright © 2023 Intel Corporation

 */



#include <linux/pci.h>

#include <linux/pnp.h>



#include <drm/drm_managed.h>



#include "i915_drv.h"

#include "intel_gmch.h"

#include "intel_pci_config.h"



static void intel_gmch_bridge_release(struct drm_device *dev, void *bridge)

{

	pci_dev_put(bridge);

}



int intel_gmch_bridge_setup(struct drm_i915_private *dev_priv)

{

	int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);



	dev_priv->gmch.pdev =

		pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));

	if (!dev_priv->gmch.pdev) {

		drm_err(&dev_priv->drm, "bridge device not found\n");

		return -EIO;

	}



	return drmm_add_action_or_reset(&dev_priv->drm, intel_gmch_bridge_release,

					dev_priv->gmch.pdev);

}



/* Allocate space for the MCH regs if needed, return nonzero on error */

static int

intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)

{

	int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;

	u32 temp_lo, temp_hi = 0;

	u64 mchbar_addr;

	int ret;



	if (GRAPHICS_VER(dev_priv) >= 4)

		pci_read_config_dword(dev_priv->gmch.pdev, reg + 4, &temp_hi);

	pci_read_config_dword(dev_priv->gmch.pdev, reg, &temp_lo);

	mchbar_addr = ((u64)temp_hi << 32) | temp_lo;



	/* If ACPI doesn't have it, assume we need to allocate it ourselves */

#ifdef CONFIG_PNP

	if (mchbar_addr &&

	    pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))

		return 0;

#endif



	/* Get some space for it */

	dev_priv->gmch.mch_res.name = "i915 MCHBAR";

	dev_priv->gmch.mch_res.flags = IORESOURCE_MEM;

	ret = pci_bus_alloc_resource(dev_priv->gmch.pdev->bus,

				     &dev_priv->gmch.mch_res,

				     MCHBAR_SIZE, MCHBAR_SIZE,

				     PCIBIOS_MIN_MEM,

				     0, pcibios_align_resource,

				     dev_priv->gmch.pdev);

	if (ret) {

		drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);

		dev_priv->gmch.mch_res.start = 0;

		return ret;

	}



	if (GRAPHICS_VER(dev_priv) >= 4)

		pci_write_config_dword(dev_priv->gmch.pdev, reg + 4,

				       upper_32_bits(dev_priv->gmch.mch_res.start));



	pci_write_config_dword(dev_priv->gmch.pdev, reg,

			       lower_32_bits(dev_priv->gmch.mch_res.start));

	return 0;

}



/* Setup MCHBAR if possible, return true if we should disable it again */

void intel_gmch_bar_setup(struct drm_i915_private *dev_priv)

{

	int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;

	u32 temp;

	bool enabled;



	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))

		return;



	dev_priv->gmch.mchbar_need_disable = false;



	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {

		pci_read_config_dword(dev_priv->gmch.pdev, DEVEN, &temp);

		enabled = !!(temp & DEVEN_MCHBAR_EN);

	} else {

		pci_read_config_dword(dev_priv->gmch.pdev, mchbar_reg, &temp);

		enabled = temp & 1;

	}



	/* If it's already enabled, don't have to do anything */

	if (enabled)

		return;



	if (intel_alloc_mchbar_resource(dev_priv))

		return;



	dev_priv->gmch.mchbar_need_disable = true;



	/* Space is allocated or reserved, so enable it. */

	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {

		pci_write_config_dword(dev_priv->gmch.pdev, DEVEN,

				       temp | DEVEN_MCHBAR_EN);

	} else {

		pci_read_config_dword(dev_priv->gmch.pdev, mchbar_reg, &temp);

		pci_write_config_dword(dev_priv->gmch.pdev, mchbar_reg, temp | 1);

	}

}



void intel_gmch_bar_teardown(struct drm_i915_private *dev_priv)

{

	int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;



	if (dev_priv->gmch.mchbar_need_disable) {

		if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {

			u32 deven_val;



			pci_read_config_dword(dev_priv->gmch.pdev, DEVEN,

					      &deven_val);

			deven_val &= ~DEVEN_MCHBAR_EN;

			pci_write_config_dword(dev_priv->gmch.pdev, DEVEN,

					       deven_val);

		} else {

			u32 mchbar_val;



			pci_read_config_dword(dev_priv->gmch.pdev, mchbar_reg,

					      &mchbar_val);

			mchbar_val &= ~1;

			pci_write_config_dword(dev_priv->gmch.pdev, mchbar_reg,

					       mchbar_val);

		}

	}



	if (dev_priv->gmch.mch_res.start)

		release_resource(&dev_priv->gmch.mch_res);

}

drivers/gpu/drm/i915/soc/intel_gmch.h

0 → 100644
+15 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

/*

 * Copyright © 2023 Intel Corporation

 */



#ifndef __INTEL_GMCH_H__

#define __INTEL_GMCH_H__



struct drm_i915_private;



int intel_gmch_bridge_setup(struct drm_i915_private *i915);

void intel_gmch_bar_setup(struct drm_i915_private *i915);

void intel_gmch_bar_teardown(struct drm_i915_private *i915);



#endif /* __INTEL_GMCH_H__ */