Commit a10a22b0 authored by Wenjing Liu's avatar Wenjing Liu Committed by Alex Deucher
Browse files

drm/amd/display: update pixel rate div in enable stream 



[why]
Pixel rate div depends on the type of encoder
that we are enabling stream with. If we swap between
HPO and DIO encoder at the time we call enable stream
for the new encoder, we must reprogram pixel rate div
based on the new encoder type.

Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7462475e

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+12 −0
Original line number Diff line number Diff line
@@ -2687,6 +2687,9 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 
	struct dccg *dccg = dc->res_pool->dccg;

	enum phyd32clk_clock_source phyd32clk;

	int dp_hpo_inst;

	struct dce_hwseq *hws = dc->hwseq;

	unsigned int k1_div = PIXEL_RATE_DIV_NA;

	unsigned int k2_div = PIXEL_RATE_DIV_NA;



	if (is_dp_128b_132b_signal(pipe_ctx)) {

		if (dc->hwseq->funcs.setup_hpo_hw_control)
@@ -2708,6 +2711,15 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 
		dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

	}



	if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {

		hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);



		dc->res_pool->dccg->funcs->set_pixel_rate_div(

			dc->res_pool->dccg,

			pipe_ctx->stream_res.tg->inst,

			k1_div, k2_div);

	}



	link_hwss->setup_stream_encoder(pipe_ctx);



	if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {