Commit a0ec2256 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: unified interfaces for message issuing and response checking 



This can avoid potential race condition between them.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5964f3fe

drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

+101 −64
Original line number Diff line number Diff line
@@ -76,7 +76,7 @@ static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr, 
		pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");

		return -EINVAL;

	}

	smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq);

	smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq, NULL);



	return 0;

}
@@ -209,7 +209,8 @@ static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clo 
		smu10_data->deep_sleep_dcefclk = clock;

		smum_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_SetMinDeepSleepDcefclk,

					smu10_data->deep_sleep_dcefclk);

					smu10_data->deep_sleep_dcefclk,

					NULL);

	}

	return 0;

}
@@ -223,7 +224,8 @@ static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t c 
		smu10_data->dcf_actual_hard_min_freq = clock;

		smum_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_SetHardMinDcefclkByFreq,

					smu10_data->dcf_actual_hard_min_freq);

					smu10_data->dcf_actual_hard_min_freq,

					NULL);

	}

	return 0;

}
@@ -237,7 +239,8 @@ static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t cloc 
		smu10_data->f_actual_hard_min_freq = clock;

		smum_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_SetHardMinFclkByFreq,

					smu10_data->f_actual_hard_min_freq);

					smu10_data->f_actual_hard_min_freq,

					NULL);

	}

	return 0;

}
@@ -250,7 +253,8 @@ static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count 
		smu10_data->num_active_display = count;

		smum_send_msg_to_smc_with_parameter(hwmgr,

				PPSMC_MSG_SetDisplayCount,

				smu10_data->num_active_display);

				smu10_data->num_active_display,

				NULL);

	}



	return 0;
@@ -273,7 +277,8 @@ static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr) 
	if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)

		return smum_send_msg_to_smc_with_parameter(hwmgr,

							   PPSMC_MSG_SetGfxCGPG,

							   true);

							   true,

							   NULL);

	else

		return 0;

}
@@ -319,7 +324,7 @@ static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr) 
	struct amdgpu_device *adev = hwmgr->adev;



	if (adev->pm.pp_feature & PP_GFXOFF_MASK) {

		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff);

		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff, NULL);



		/* confirm gfx is back to "on" state */

		while (!smu10_is_gfx_on(hwmgr))
@@ -339,7 +344,7 @@ static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr) 
	struct amdgpu_device *adev = hwmgr->adev;



	if (adev->pm.pp_feature & PP_GFXOFF_MASK)

		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff);

		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff, NULL);



	return 0;

}
@@ -474,12 +479,10 @@ static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr) 
	smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,

					ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);



	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency);

	result = smum_get_argument(hwmgr);

	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &result);

	smu10_data->gfx_min_freq_limit = result / 10 * 1000;



	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency);

	result = smum_get_argument(hwmgr);

	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &result);

	smu10_data->gfx_max_freq_limit = result / 10 * 1000;



	return 0;
@@ -583,116 +586,148 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, 
	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetHardMinGfxClk,

						data->gfx_max_freq_limit/100);

						data->gfx_max_freq_limit/100,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetHardMinFclkByFreq,

						SMU10_UMD_PSTATE_PEAK_FCLK);

						SMU10_UMD_PSTATE_PEAK_FCLK,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetHardMinSocclkByFreq,

						SMU10_UMD_PSTATE_PEAK_SOCCLK);

						SMU10_UMD_PSTATE_PEAK_SOCCLK,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetHardMinVcn,

						SMU10_UMD_PSTATE_VCE);

						SMU10_UMD_PSTATE_VCE,

						NULL);



		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetSoftMaxGfxClk,

						data->gfx_max_freq_limit/100);

						data->gfx_max_freq_limit/100,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetSoftMaxFclkByFreq,

						SMU10_UMD_PSTATE_PEAK_FCLK);

						SMU10_UMD_PSTATE_PEAK_FCLK,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetSoftMaxSocclkByFreq,

						SMU10_UMD_PSTATE_PEAK_SOCCLK);

						SMU10_UMD_PSTATE_PEAK_SOCCLK,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetSoftMaxVcn,

						SMU10_UMD_PSTATE_VCE);

						SMU10_UMD_PSTATE_VCE,

						NULL);

		break;

	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetHardMinGfxClk,

						min_sclk);

						min_sclk,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetSoftMaxGfxClk,

						min_sclk);

						min_sclk,

						NULL);

		break;

	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetHardMinFclkByFreq,

						min_mclk);

						min_mclk,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetSoftMaxFclkByFreq,

						min_mclk);

						min_mclk,

						NULL);

		break;

	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetHardMinGfxClk,

						SMU10_UMD_PSTATE_GFXCLK);

						SMU10_UMD_PSTATE_GFXCLK,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetHardMinFclkByFreq,

						SMU10_UMD_PSTATE_FCLK);

						SMU10_UMD_PSTATE_FCLK,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetHardMinSocclkByFreq,

						SMU10_UMD_PSTATE_SOCCLK);

						SMU10_UMD_PSTATE_SOCCLK,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetHardMinVcn,

						SMU10_UMD_PSTATE_VCE);

						SMU10_UMD_PSTATE_VCE,

						NULL);



		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetSoftMaxGfxClk,

						SMU10_UMD_PSTATE_GFXCLK);

						SMU10_UMD_PSTATE_GFXCLK,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetSoftMaxFclkByFreq,

						SMU10_UMD_PSTATE_FCLK);

						SMU10_UMD_PSTATE_FCLK,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetSoftMaxSocclkByFreq,

						SMU10_UMD_PSTATE_SOCCLK);

						SMU10_UMD_PSTATE_SOCCLK,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetSoftMaxVcn,

						SMU10_UMD_PSTATE_VCE);

						SMU10_UMD_PSTATE_VCE,

						NULL);

		break;

	case AMD_DPM_FORCED_LEVEL_AUTO:

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetHardMinGfxClk,

						min_sclk);

						min_sclk,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetHardMinFclkByFreq,

						hwmgr->display_config->num_display > 3 ?

						SMU10_UMD_PSTATE_PEAK_FCLK :

						min_mclk);

						min_mclk,

						NULL);



		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetHardMinSocclkByFreq,

						SMU10_UMD_PSTATE_MIN_SOCCLK);

						SMU10_UMD_PSTATE_MIN_SOCCLK,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetHardMinVcn,

						SMU10_UMD_PSTATE_MIN_VCE);

						SMU10_UMD_PSTATE_MIN_VCE,

						NULL);



		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetSoftMaxGfxClk,

						data->gfx_max_freq_limit/100);

						data->gfx_max_freq_limit/100,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetSoftMaxFclkByFreq,

						SMU10_UMD_PSTATE_PEAK_FCLK);

						SMU10_UMD_PSTATE_PEAK_FCLK,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetSoftMaxSocclkByFreq,

						SMU10_UMD_PSTATE_PEAK_SOCCLK);

						SMU10_UMD_PSTATE_PEAK_SOCCLK,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetSoftMaxVcn,

						SMU10_UMD_PSTATE_VCE);

						SMU10_UMD_PSTATE_VCE,

						NULL);

		break;

	case AMD_DPM_FORCED_LEVEL_LOW:

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetHardMinGfxClk,

						data->gfx_min_freq_limit/100);

						data->gfx_min_freq_limit/100,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetSoftMaxGfxClk,

						data->gfx_min_freq_limit/100);

						data->gfx_min_freq_limit/100,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetHardMinFclkByFreq,

						min_mclk);

						min_mclk,

						NULL);

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetSoftMaxFclkByFreq,

						min_mclk);

						min_mclk,

						NULL);

		break;

	case AMD_DPM_FORCED_LEVEL_MANUAL:

	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
@@ -844,13 +879,15 @@ static int smu10_force_clock_level(struct pp_hwmgr *hwmgr, 
						PPSMC_MSG_SetHardMinGfxClk,

						low == 2 ? data->gfx_max_freq_limit/100 :

						low == 1 ? SMU10_UMD_PSTATE_GFXCLK :

						data->gfx_min_freq_limit/100);

						data->gfx_min_freq_limit/100,

						NULL);



		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetSoftMaxGfxClk,

						high == 0 ? data->gfx_min_freq_limit/100 :

						high == 1 ? SMU10_UMD_PSTATE_GFXCLK :

						data->gfx_max_freq_limit/100);

						data->gfx_max_freq_limit/100,

						NULL);

		break;



	case PP_MCLK:
@@ -859,11 +896,13 @@ static int smu10_force_clock_level(struct pp_hwmgr *hwmgr, 


		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetHardMinFclkByFreq,

						mclk_table->entries[low].clk/100);

						mclk_table->entries[low].clk/100,

						NULL);



		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_SetSoftMaxFclkByFreq,

						mclk_table->entries[high].clk/100);

						mclk_table->entries[high].clk/100,

						NULL);

		break;



	case PP_PCIE:
@@ -883,8 +922,7 @@ static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr, 


	switch (type) {

	case PP_SCLK:

		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);

		now = smum_get_argument(hwmgr);

		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &now);



	/* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */

		if (now == data->gfx_max_freq_limit/100)
@@ -905,8 +943,7 @@ static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr, 
					i == 2 ? "*" : "");

		break;

	case PP_MCLK:

		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);

		now = smum_get_argument(hwmgr);

		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &now);



		for (i = 0; i < mclk_table->count; i++)

			size += sprintf(buf + size, "%d: %uMhz %s\n",
@@ -1117,15 +1154,13 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx, 


	switch (idx) {

	case AMDGPU_PP_SENSOR_GFX_SCLK:

		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);

		sclk = smum_get_argument(hwmgr);

		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &sclk);

			/* in units of 10KHZ */

		*((uint32_t *)value) = sclk * 100;

		*size = 4;

		break;

	case AMDGPU_PP_SENSOR_GFX_MCLK:

		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);

		mclk = smum_get_argument(hwmgr);

		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &mclk);

			/* in units of 10KHZ */

		*((uint32_t *)value) = mclk * 100;

		*size = 4;
@@ -1161,20 +1196,20 @@ static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, 
static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr)

{



	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SetRccPfcPmeRestoreRegister);

	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SetRccPfcPmeRestoreRegister, NULL);

}



static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr)

{

	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub);

	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub, NULL);

}



static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate)

{

	if (gate)

		return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerDownSdma);

		return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerDownSdma, NULL);

	else

		return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerUpSdma);

		return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerUpSdma, NULL);

}



static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
@@ -1186,11 +1221,11 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate) 
						AMD_IP_BLOCK_TYPE_VCN,

						AMD_PG_STATE_GATE);

		smum_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_PowerDownVcn, 0);

					PPSMC_MSG_PowerDownVcn, 0, NULL);

		smu10_data->vcn_power_gated = true;

	} else {

		smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_PowerUpVcn, 0);

						PPSMC_MSG_PowerUpVcn, 0, NULL);

		amdgpu_device_ip_set_powergating_state(hwmgr->adev,

						AMD_IP_BLOCK_TYPE_VCN,

						AMD_PG_STATE_UNGATE);
@@ -1299,7 +1334,8 @@ static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uin 
		hwmgr->gfxoff_state_changed_by_workload = true;

	}

	result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ActiveProcessNotify,

						1 << workload_type);

						1 << workload_type,

						NULL);

	if (!result)

		hwmgr->power_profile_mode = input[size];

	if (workload_type && hwmgr->gfxoff_state_changed_by_workload) {
@@ -1314,7 +1350,8 @@ static int smu10_asic_reset(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mod 
{

	return smum_send_msg_to_smc_with_parameter(hwmgr,

						   PPSMC_MSG_DeviceDriverReset,

						   mode);

						   mode,

						   NULL);

}



static const struct pp_hwmgr_func smu10_hwmgr_funcs = {

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c

+34 −27
Original line number Diff line number Diff line
@@ -29,14 +29,16 @@ static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) 
{

	return smum_send_msg_to_smc(hwmgr, enable ?

			PPSMC_MSG_UVDDPM_Enable :

			PPSMC_MSG_UVDDPM_Disable);

			PPSMC_MSG_UVDDPM_Disable,

			NULL);

}



static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)

{

	return smum_send_msg_to_smc(hwmgr, enable ?

			PPSMC_MSG_VCEDPM_Enable :

			PPSMC_MSG_VCEDPM_Disable);

			PPSMC_MSG_VCEDPM_Disable,

			NULL);

}



static int smu7_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
@@ -57,7 +59,8 @@ int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr) 
{

	if (phm_cf_want_uvd_power_gating(hwmgr))

		return smum_send_msg_to_smc(hwmgr,

				PPSMC_MSG_UVDPowerOFF);

				PPSMC_MSG_UVDPowerOFF,

				NULL);

	return 0;

}
@@ -67,10 +70,10 @@ static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr) 
		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,

				  PHM_PlatformCaps_UVDDynamicPowerGating)) {

			return smum_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_UVDPowerON, 1);

					PPSMC_MSG_UVDPowerON, 1, NULL);

		} else {

			return smum_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_UVDPowerON, 0);

					PPSMC_MSG_UVDPowerON, 0, NULL);

		}

	}
@@ -81,7 +84,8 @@ static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr) 
{

	if (phm_cf_want_vce_power_gating(hwmgr))

		return smum_send_msg_to_smc(hwmgr,

				PPSMC_MSG_VCEPowerOFF);

				PPSMC_MSG_VCEPowerOFF,

				NULL);

	return 0;

}
@@ -89,7 +93,8 @@ static int smu7_powerup_vce(struct pp_hwmgr *hwmgr) 
{

	if (phm_cf_want_vce_power_gating(hwmgr))

		return smum_send_msg_to_smc(hwmgr,

				PPSMC_MSG_VCEPowerON);

				PPSMC_MSG_VCEPowerON,

				NULL);

	return 0;

}
@@ -181,7 +186,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, 
				value = CG_GFX_CGCG_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr, msg, value))

						hwmgr, msg, value, NULL))

					return -EINVAL;

			}

			if (PP_STATE_SUPPORT_LS & *msg_id) {
@@ -191,7 +196,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, 
				value = CG_GFX_CGLS_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr, msg, value))

						hwmgr, msg, value, NULL))

					return -EINVAL;

			}

			break;
@@ -204,7 +209,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, 
				value = CG_GFX_3DCG_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr, msg, value))

						hwmgr, msg, value, NULL))

					return -EINVAL;

			}
@@ -215,7 +220,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, 
				value = CG_GFX_3DLS_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr, msg, value))

						hwmgr, msg, value, NULL))

					return -EINVAL;

			}

			break;
@@ -228,7 +233,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, 
				value = CG_GFX_RLC_LS_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr, msg, value))

						hwmgr, msg, value, NULL))

					return -EINVAL;

			}

			break;
@@ -241,7 +246,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, 
				value = CG_GFX_CP_LS_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr, msg, value))

						hwmgr, msg, value, NULL))

					return -EINVAL;

			}

			break;
@@ -255,7 +260,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, 
						CG_GFX_OTHERS_MGCG_MASK);



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr, msg, value))

						hwmgr, msg, value, NULL))

					return -EINVAL;

			}

			break;
@@ -275,7 +280,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, 
				value = CG_SYS_BIF_MGCG_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr, msg, value))

						hwmgr, msg, value, NULL))

					return -EINVAL;

			}

			if  (PP_STATE_SUPPORT_LS & *msg_id) {
@@ -285,7 +290,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, 
				value = CG_SYS_BIF_MGLS_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr, msg, value))

						hwmgr, msg, value, NULL))

					return -EINVAL;

			}

			break;
@@ -298,7 +303,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, 
				value = CG_SYS_MC_MGCG_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr, msg, value))

						hwmgr, msg, value, NULL))

					return -EINVAL;

			}
@@ -309,7 +314,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, 
				value = CG_SYS_MC_MGLS_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr, msg, value))

						hwmgr, msg, value, NULL))

					return -EINVAL;

			}

			break;
@@ -322,7 +327,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, 
				value = CG_SYS_DRM_MGCG_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr, msg, value))

						hwmgr, msg, value, NULL))

					return -EINVAL;

			}

			if (PP_STATE_SUPPORT_LS & *msg_id) {
@@ -332,7 +337,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, 
				value = CG_SYS_DRM_MGLS_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr, msg, value))

						hwmgr, msg, value, NULL))

					return -EINVAL;

			}

			break;
@@ -345,7 +350,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, 
				value = CG_SYS_HDP_MGCG_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr, msg, value))

						hwmgr, msg, value, NULL))

					return -EINVAL;

			}
@@ -356,7 +361,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, 
				value = CG_SYS_HDP_MGLS_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr, msg, value))

						hwmgr, msg, value, NULL))

					return -EINVAL;

			}

			break;
@@ -369,7 +374,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, 
				value = CG_SYS_SDMA_MGCG_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr, msg, value))

						hwmgr, msg, value, NULL))

					return -EINVAL;

			}
@@ -380,7 +385,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, 
				value = CG_SYS_SDMA_MGLS_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr, msg, value))

						hwmgr, msg, value, NULL))

					return -EINVAL;

			}

			break;
@@ -393,7 +398,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, 
				value = CG_SYS_ROM_MASK;



				if (smum_send_msg_to_smc_with_parameter(

						hwmgr, msg, value))

						hwmgr, msg, value, NULL))

					return -EINVAL;

			}

			break;
@@ -423,8 +428,10 @@ int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable) 
	if (enable)

		return smum_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_GFX_CU_PG_ENABLE,

					adev->gfx.cu_info.number);

					adev->gfx.cu_info.number,

					NULL);

	else

		return smum_send_msg_to_smc(hwmgr,

				PPSMC_MSG_GFX_CU_PG_DISABLE);

				PPSMC_MSG_GFX_CU_PG_DISABLE,

				NULL);

}

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

+79 −56

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c

+28 −12
Original line number Diff line number Diff line
@@ -887,7 +887,10 @@ static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable) 
	didt_block |= block_en << TCP_Enable_SHIFT;



	if (enable)

		result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_Didt_Block_Function, didt_block);

		result = smum_send_msg_to_smc_with_parameter(hwmgr,

						PPSMC_MSG_Didt_Block_Function,

						didt_block,

						NULL);



	return result;

}
@@ -1009,7 +1012,8 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr) 


		if (hwmgr->chip_id == CHIP_POLARIS11) {

			result = smum_send_msg_to_smc(hwmgr,

						(uint16_t)(PPSMC_MSG_EnableDpmDidt));

						(uint16_t)(PPSMC_MSG_EnableDpmDidt),

						NULL);

			PP_ASSERT_WITH_CODE((0 == result),

					"Failed to enable DPM DIDT.", goto error);

		}
@@ -1042,7 +1046,8 @@ int smu7_disable_didt_config(struct pp_hwmgr *hwmgr) 
				goto error);

		if (hwmgr->chip_id == CHIP_POLARIS11) {

			result = smum_send_msg_to_smc(hwmgr,

						(uint16_t)(PPSMC_MSG_DisableDpmDidt));

						(uint16_t)(PPSMC_MSG_DisableDpmDidt),

						NULL);

			PP_ASSERT_WITH_CODE((0 == result),

					"Failed to disable DPM DIDT.", goto error);

		}
@@ -1063,7 +1068,8 @@ int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr) 
	if (PP_CAP(PHM_PlatformCaps_CAC)) {

		int smc_result;

		smc_result = smum_send_msg_to_smc(hwmgr,

				(uint16_t)(PPSMC_MSG_EnableCac));

				(uint16_t)(PPSMC_MSG_EnableCac),

				NULL);

		PP_ASSERT_WITH_CODE((0 == smc_result),

				"Failed to enable CAC in SMC.", result = -1);
@@ -1079,7 +1085,8 @@ int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr) 


	if (PP_CAP(PHM_PlatformCaps_CAC) && data->cac_enabled) {

		int smc_result = smum_send_msg_to_smc(hwmgr,

				(uint16_t)(PPSMC_MSG_DisableCac));

				(uint16_t)(PPSMC_MSG_DisableCac),

				NULL);

		PP_ASSERT_WITH_CODE((smc_result == 0),

				"Failed to disable CAC in SMC.", result = -1);
@@ -1095,7 +1102,9 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) 
	if (data->power_containment_features &

			POWERCONTAINMENT_FEATURE_PkgPwrLimit)

		return smum_send_msg_to_smc_with_parameter(hwmgr,

				PPSMC_MSG_PkgPwrSetLimit, n<<8);

				PPSMC_MSG_PkgPwrSetLimit,

				n<<8,

				NULL);

	return 0;

}
@@ -1103,7 +1112,9 @@ static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *hwmgr, 
						uint32_t target_tdp)

{

	return smum_send_msg_to_smc_with_parameter(hwmgr,

			PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);

			PPSMC_MSG_OverDriveSetTargetTdp,

			target_tdp,

			NULL);

}



int smu7_enable_power_containment(struct pp_hwmgr *hwmgr)
@@ -1124,7 +1135,8 @@ int smu7_enable_power_containment(struct pp_hwmgr *hwmgr) 
	if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {

		if (data->enable_tdc_limit_feature) {

			smc_result = smum_send_msg_to_smc(hwmgr,

					(uint16_t)(PPSMC_MSG_TDCLimitEnable));

					(uint16_t)(PPSMC_MSG_TDCLimitEnable),

					NULL);

			PP_ASSERT_WITH_CODE((0 == smc_result),

					"Failed to enable TDCLimit in SMC.", result = -1;);

			if (0 == smc_result)
@@ -1134,7 +1146,8 @@ int smu7_enable_power_containment(struct pp_hwmgr *hwmgr) 


		if (data->enable_pkg_pwr_tracking_feature) {

			smc_result = smum_send_msg_to_smc(hwmgr,

					(uint16_t)(PPSMC_MSG_PkgPwrLimitEnable));

					(uint16_t)(PPSMC_MSG_PkgPwrLimitEnable),

					NULL);

			PP_ASSERT_WITH_CODE((0 == smc_result),

					"Failed to enable PkgPwrTracking in SMC.", result = -1;);

			if (0 == smc_result) {
@@ -1163,7 +1176,8 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr) 
		if (data->power_containment_features &

				POWERCONTAINMENT_FEATURE_TDCLimit) {

			smc_result = smum_send_msg_to_smc(hwmgr,

					(uint16_t)(PPSMC_MSG_TDCLimitDisable));

					(uint16_t)(PPSMC_MSG_TDCLimitDisable),

					NULL);

			PP_ASSERT_WITH_CODE((smc_result == 0),

					"Failed to disable TDCLimit in SMC.",

					result = smc_result);
@@ -1172,7 +1186,8 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr) 
		if (data->power_containment_features &

				POWERCONTAINMENT_FEATURE_DTE) {

			smc_result = smum_send_msg_to_smc(hwmgr,

					(uint16_t)(PPSMC_MSG_DisableDTE));

					(uint16_t)(PPSMC_MSG_DisableDTE),

					NULL);

			PP_ASSERT_WITH_CODE((smc_result == 0),

					"Failed to disable DTE in SMC.",

					result = smc_result);
@@ -1181,7 +1196,8 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr) 
		if (data->power_containment_features &

				POWERCONTAINMENT_FEATURE_PkgPwrLimit) {

			smc_result = smum_send_msg_to_smc(hwmgr,

					(uint16_t)(PPSMC_MSG_PkgPwrLimitDisable));

					(uint16_t)(PPSMC_MSG_PkgPwrLimitDisable),

					NULL);

			PP_ASSERT_WITH_CODE((smc_result == 0),

					"Failed to disable PkgPwrTracking in SMC.",

					result = smc_result);

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c

+7 −6
Original line number Diff line number Diff line
@@ -152,7 +152,7 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) 


	if (PP_CAP(PHM_PlatformCaps_ODFuzzyFanControlSupport)) {

		result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_StartFanControl,

					FAN_CONTROL_FUZZY);

					FAN_CONTROL_FUZZY, NULL);



		if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM))

			hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr,
@@ -165,7 +165,7 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) 


	} else {

		result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_StartFanControl,

					FAN_CONTROL_TABLE);

					FAN_CONTROL_TABLE, NULL);

	}



	if (!result && hwmgr->thermal_controller.
@@ -173,7 +173,8 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) 
		result = smum_send_msg_to_smc_with_parameter(hwmgr,

				PPSMC_MSG_SetFanTemperatureTarget,

				hwmgr->thermal_controller.

				advanceFanControlParameters.ucTargetTemperature);

				advanceFanControlParameters.ucTargetTemperature,

				NULL);

	hwmgr->fan_ctrl_enabled = true;



	return result;
@@ -183,7 +184,7 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) 
int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)

{

	hwmgr->fan_ctrl_enabled = false;

	return smum_send_msg_to_smc(hwmgr, PPSMC_StopFanControl);

	return smum_send_msg_to_smc(hwmgr, PPSMC_StopFanControl, NULL);

}



/**
@@ -372,7 +373,7 @@ static void smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr) 
			CG_THERMAL_INT, THERM_INT_MASK, alert);



	/* send message to SMU to enable internal thermal interrupts */

	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Enable);

	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Enable, NULL);

}



/**
@@ -390,7 +391,7 @@ int smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr) 
			CG_THERMAL_INT, THERM_INT_MASK, alert);



	/* send message to SMU to disable internal thermal interrupts */

	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Disable);

	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Disable, NULL);

}



/**