Commit a0d2a2c6 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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clk: renesas: r9a07g044: Add clock and reset entry for SCI1 



Add clock and reset entry for SCI1 interface.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211103160537.32253-1-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 099ee032

drivers/clk/renesas/r9a07g044-cpg.c

+3 −0
Original line number Diff line number Diff line
@@ -217,6 +217,8 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { 
				0x584, 4),

	DEF_MOD("sci0",		R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,

				0x588, 0),

	DEF_MOD("sci1",		R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0,

				0x588, 1),

	DEF_MOD("canfd",	R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,

				0x594, 0),

	DEF_MOD("gpio",		R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
@@ -256,6 +258,7 @@ static struct rzg2l_reset r9a07g044_resets[] = { 
	DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),

	DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),

	DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),

	DEF_RST(R9A07G044_SCI1_RST, 0x888, 1),

	DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),

	DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),

	DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),