Commit a0c30cd7 authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Vinod Koul
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phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy" 



Instead of having separate structure members for each input clock, add
an array for the input clocks within "struct cdns_sierra_phy". This is
in preparation for adding more input clocks required for supporting
additional clock combination.

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: default avatarSwapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210319124128.13308-10-kishon@ti.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent fd7abc3c

drivers/phy/cadence/phy-cadence-sierra.c

+15 −10
Original line number Diff line number Diff line
@@ -144,6 +144,13 @@ 
#define SIERRA_MAX_LANES				16

#define PLL_LOCK_TIME					100000



#define CDNS_SIERRA_INPUT_CLOCKS			3

enum cdns_sierra_clock_input {

	PHY_CLK,

	CMN_REFCLK_DIG_DIV,

	CMN_REFCLK1_DIG_DIV,

};



static const struct reg_field macro_id_type =

				REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);

static const struct reg_field phy_pll_cfg_1 =
@@ -197,9 +204,7 @@ struct cdns_sierra_phy { 
	struct regmap_field *macro_id_type;

	struct regmap_field *phy_pll_cfg_1;

	struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];

	struct clk *clk;

	struct clk *cmn_refclk_dig_div;

	struct clk *cmn_refclk1_dig_div;

	struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS];

	int nsubnodes;

	u32 num_lanes;

	bool autoconf;
@@ -281,8 +286,8 @@ static int cdns_sierra_phy_init(struct phy *gphy) 
	if (phy->autoconf)

		return 0;



	clk_set_rate(phy->cmn_refclk_dig_div, 25000000);

	clk_set_rate(phy->cmn_refclk1_dig_div, 25000000);

	clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000);

	clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);

	if (ins->phy_type == PHY_TYPE_PCIE) {

		num_cmn_regs = phy->init_data->pcie_cmn_regs;

		num_ln_regs = phy->init_data->pcie_ln_regs;
@@ -488,7 +493,7 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, 
		dev_err(dev, "failed to get clock phy_clk\n");

		return PTR_ERR(clk);

	}

	sp->clk = clk;

	sp->input_clks[PHY_CLK] = clk;



	clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");

	if (IS_ERR(clk)) {
@@ -496,7 +501,7 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, 
		ret = PTR_ERR(clk);

		return ret;

	}

	sp->cmn_refclk_dig_div = clk;

	sp->input_clks[CMN_REFCLK_DIG_DIV] = clk;



	clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");

	if (IS_ERR(clk)) {
@@ -504,7 +509,7 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, 
		ret = PTR_ERR(clk);

		return ret;

	}

	sp->cmn_refclk1_dig_div = clk;

	sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk;



	return 0;

}
@@ -585,7 +590,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	ret = clk_prepare_enable(sp->clk);

	ret = clk_prepare_enable(sp->input_clks[PHY_CLK]);

	if (ret)

		return ret;
@@ -662,7 +667,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) 
		reset_control_put(sp->phys[i].lnk_rst);

	of_node_put(child);

clk_disable:

	clk_disable_unprepare(sp->clk);

	clk_disable_unprepare(sp->input_clks[PHY_CLK]);

	reset_control_assert(sp->apb_rst);

	return ret;

}