Unverified Commit a070e6da authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!15572 tlbi: fix the problem of incorrect TLB flashing 

Merge Pull Request from: @zhao-lichang 
 
1. kernel: tlbi: fix the problem of incorrect TLB flashing
2. KVM: arm64: add a new cmdline parameter "kvm-arm.hcr_nofb" for users and setting it at boot time allows all vcpus running without HCR_EL2.FB.

NOTE(Important)
This feature is used for learning and debugging only. Please don't enable it on commercial products.
It will not be synced to the LTS version.

https://gitee.com/openeuler/kernel/issues/IBU2Y1 
 
Link:https://gitee.com/openeuler/kernel/pulls/15572

 

Reviewed-by: default avatarZhang Jianhua <chris.zjh@huawei.com>
Reviewed-by: default avatarZenghui Yu <yuzenghui@huawei.com>
Reviewed-by: default avatarLiu Chao <liuchao173@huawei.com>
Signed-off-by: default avatarZhang Peng <zhangpeng362@huawei.com>
parents 3e001e96 f69080d2

arch/arm64/Kconfig

+2 −4
Original line number Diff line number Diff line
@@ -2679,10 +2679,8 @@ config ARM64_TLBI_IPI 
	depends on ARM64

	default n

	help

	  adds new boot parameter 'disable_tlbflush_is' to disable TLB flush

	  within the same inner shareable domain for performance tuning.



	  When this new parameter is specified, TLB entry is invalidated by

	  Disable TLB flush within the same inner shareable domain for performance

	  tuning. When this new parameter is specified, TLB entry is invalidated by

	  __tlbi(aside1, asid) only on the CPUs specified by mm_cpumask(mm).



	  By using TLB.IS, all CPUs within the same inner shareable domain

arch/arm64/configs/openeuler_defconfig

+2 −1
Original line number Diff line number Diff line
@@ -776,6 +776,7 @@ CONFIG_KVM_ARM_MULTI_LPI_TRANSLATE_CACHE=y 
CONFIG_ARCH_VCPU_STAT=y

CONFIG_VIRT_VTIMER_IRQ_BYPASS=y

CONFIG_CPU_MITIGATIONS=y

# CONFIG_ARM64_KVM_HCR_NOFB is not set



#

# Hardware Assisted OS Compartmentalization(HAOC)
@@ -3945,7 +3946,7 @@ CONFIG_PINMUX=y 
CONFIG_PINCONF=y

CONFIG_GENERIC_PINCONF=y

# CONFIG_DEBUG_PINCTRL is not set

CONFIG_PINCTRL_AMD=m

CONFIG_PINCTRL_AMD=y

# CONFIG_PINCTRL_CY8C95X0 is not set

# CONFIG_PINCTRL_MCP23S08 is not set

# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set

arch/arm64/include/asm/kvm_emulate.h

+9 −0
Original line number Diff line number Diff line
@@ -66,6 +66,10 @@ static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu) 
}

#endif



#ifdef CONFIG_ARM64_KVM_HCR_NOFB

extern bool kvm_hcr_nofb;

#endif



static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)

{

	vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS;
@@ -101,6 +105,11 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) 


	if (kvm_has_mte(vcpu->kvm))

		vcpu->arch.hcr_el2 |= HCR_ATA;



#ifdef CONFIG_ARM64_KVM_HCR_NOFB

	if (unlikely(kvm_hcr_nofb))

		vcpu->arch.hcr_el2 &= ~HCR_FB;

#endif

}



static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu)

arch/arm64/include/asm/mmu_context.h

+6 −8
Original line number Diff line number Diff line
@@ -249,6 +249,11 @@ enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 


static inline void __switch_mm(struct mm_struct *next)

{

#ifdef CONFIG_ARM64_TLBI_IPI

	unsigned int cpu = smp_processor_id();



	cpumask_set_cpu(cpu, mm_cpumask(next));

#endif

	/*

	 * init_mm.pgd does not contain any user mappings and it is always

	 * active for kernel addresses in TTBR1. Just set the reserved TTBR0.
@@ -265,15 +270,8 @@ static inline void 
switch_mm(struct mm_struct *prev, struct mm_struct *next,

	  struct task_struct *tsk)

{

	if (prev != next) {

	if (prev != next)

		__switch_mm(next);

#ifdef CONFIG_ARM64_TLBI_IPI

		if (unlikely(test_tlbi_ipi_switch())) {

			cpumask_clear_cpu(smp_processor_id(), mm_cpumask(prev));

			local_flush_tlb_mm(prev);

		}

#endif

	}



	/*

	 * Update the saved TTBR0_EL1 of the scheduled-in task as the previous

arch/arm64/include/asm/pgtable.h

+0 −4
Original line number Diff line number Diff line
@@ -946,11 +946,7 @@ static inline int __ptep_clear_flush_young(struct vm_area_struct *vma, 
		 * context-switch, which provides a DSB to complete the TLB

		 * invalidation.

		 */

#ifdef CONFIG_ARM64_TLBI_IPI

		flush_tlb_page_nosync_ipi(vma, address);

#else

		flush_tlb_page_nosync(vma, address);

#endif

	}



	return young;