dt-bindings: memory-controllers: nuvoton: Add NPCM memory controller

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/nuvoton,npcm-memory-controller.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Nuvoton NPCM Memory Controller

maintainers:

  - Marvin Lin <kflin@nuvoton.com>

  - Stanley Chu <yschu@nuvoton.com>

description: |

  The Nuvoton BMC SoC supports DDR4 memory with or without ECC (error correction

  check).

  The memory controller supports single bit error correction, double bit error

  detection (in-line ECC in which a section (1/8th) of the memory device used to

  store data is used for ECC storage).

  Note, the bootloader must configure ECC mode for the memory controller.

properties:

  compatible:

    enum:

      - nuvoton,npcm750-memory-controller

      - nuvoton,npcm845-memory-controller

  reg:

    maxItems: 1

  interrupts:

    maxItems: 1

required:

  - compatible

  - reg

  - interrupts

additionalProperties: false

examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    mc: memory-controller@f0824000 {

        compatible = "nuvoton,npcm750-memory-controller";

        reg = <0xf0824000 0x1000>;

        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

    };