Commit a01be32f authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Dinh Nguyen
Browse files

clk: socfpga: build together Stratix 10, Agilex and N5X clock drivers 



On a multiplatform kernel there is little benefit in splitting each
clock driver per platform because space savings are minimal.  Such split
also complicates the code, especially after adding compile testing.

Build all arm64 Intel SoCFPGA clocks together with one entry in
Makefile.  This also removed duplicated line in the Makefile (selecting
common part of clocks per platform).

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent 3409fb09

drivers/clk/socfpga/Kconfig

+3 −3
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# SPDX-License-Identifier: GPL-2.0

# SPDX-License-Identifier: GPL-2.0

config CLK_INTEL_SOCFPGA64

config CLK_INTEL_SOCFPGA64

	bool

	bool

	# Intel Agilex / N5X clock controller support

	# Intel Stratix / Agilex / N5X clock controller support

	default (ARCH_AGILEX || ARCH_N5X)

	default (ARCH_AGILEX || ARCH_N5X || ARCH_STRATIX10)

	depends on ARCH_AGILEX || ARCH_N5X
 
	depends on ARCH_AGILEX || ARCH_N5X || ARCH_STRATIX10

drivers/clk/socfpga/Makefile

+3 −4
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# SPDX-License-Identifier: GPL-2.0

# SPDX-License-Identifier: GPL-2.0

obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o

obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o

obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o

obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o

obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o

obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-s10.o \

obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o

				     clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o \

obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-agilex.o

				     clk-agilex.o
 
obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o