Commit a00d077a authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

clk: renesas: r8a7740: Remove r8a7740_cpg.reg 



The register block base pointer as stored in the reg member of the
r8a7740_cpg structure is only used during initialization.  Hence move
it to a local variable, and pass it as a parameter to
r8a7740_cpg_register_clock().

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/7ec676bcc36ef1eda02c2db328c527fc5fd44e99.1654694831.git.geert+renesas@glider.be
parent 65d012e4

drivers/clk/renesas/clk-r8a7740.c

+10 −10
Original line number Diff line number Diff line
@@ -18,7 +18,6 @@ 
struct r8a7740_cpg {

	struct clk_onecell_data data;

	spinlock_t lock;

	void __iomem *reg;

};



#define CPG_FRQCRA	0x00
@@ -61,7 +60,7 @@ static u32 cpg_mode __initdata; 


static struct clk * __init

r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,

			     const char *name)

			   void __iomem *base, const char *name)

{

	const struct clk_div_table *table = NULL;

	const char *parent_name;
@@ -96,20 +95,20 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, 
		 * clock implementation and we currently have no need to change

		 * the multiplier value.

		 */

		u32 value = readl(cpg->reg + CPG_FRQCRC);

		u32 value = readl(base + CPG_FRQCRC);

		parent_name = "system";

		mult = ((value >> 24) & 0x7f) + 1;

	} else if (!strcmp(name, "pllc1")) {

		u32 value = readl(cpg->reg + CPG_FRQCRA);

		u32 value = readl(base + CPG_FRQCRA);

		parent_name = "system";

		mult = ((value >> 24) & 0x7f) + 1;

		div = 2;

	} else if (!strcmp(name, "pllc2")) {

		u32 value = readl(cpg->reg + CPG_PLLC2CR);

		u32 value = readl(base + CPG_PLLC2CR);

		parent_name = "system";

		mult = ((value >> 24) & 0x3f) + 1;

	} else if (!strcmp(name, "usb24s")) {

		u32 value = readl(cpg->reg + CPG_USBCKCR);

		u32 value = readl(base + CPG_USBCKCR);

		if (value & BIT(7))

			/* extal2 */

			parent_name = of_clk_get_parent_name(np, 1);
@@ -137,7 +136,7 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, 
						 mult, div);

	} else {

		return clk_register_divider_table(NULL, name, parent_name, 0,

						  cpg->reg + reg, shift, 4, 0,

						  base + reg, shift, 4, 0,

						  table, &cpg->lock);

	}

}
@@ -145,6 +144,7 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, 
static void __init r8a7740_cpg_clocks_init(struct device_node *np)

{

	struct r8a7740_cpg *cpg;

	void __iomem *base;

	struct clk **clks;

	unsigned int i;

	int num_clks;
@@ -172,8 +172,8 @@ static void __init r8a7740_cpg_clocks_init(struct device_node *np) 
	cpg->data.clks = clks;

	cpg->data.clk_num = num_clks;



	cpg->reg = of_iomap(np, 0);

	if (WARN_ON(cpg->reg == NULL))

	base = of_iomap(np, 0);

	if (WARN_ON(base == NULL))

		return;



	for (i = 0; i < num_clks; ++i) {
@@ -183,7 +183,7 @@ static void __init r8a7740_cpg_clocks_init(struct device_node *np) 
		of_property_read_string_index(np, "clock-output-names", i,

					      &name);



		clk = r8a7740_cpg_register_clock(np, cpg, name);

		clk = r8a7740_cpg_register_clock(np, cpg, base, name);

		if (IS_ERR(clk))

			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",

			       __func__, np, name, PTR_ERR(clk));