Commit 9fd96c06 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915/gt: Move move context layout registers and offsets to lrc_reg.h 



Cleanup intel_lrc.h by moving some of the residual common register
definitions into intel_lrc_reg.h, prior to rebranding and splitting off
the submission backends.

v2: keep the SCHEDULE enum in the old file, since it is specific to the
gvt usage of the execlists submission backend (John)

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> #v2
Cc: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201209233618.4287-1-chris@chris-wilson.co.uk
parent 51c87fa6

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+1 −1
Original line number Diff line number Diff line
@@ -36,7 +36,7 @@ 
#include "intel_gt.h"

#include "intel_gt_requests.h"

#include "intel_gt_pm.h"

#include "intel_lrc.h"

#include "intel_lrc_reg.h"

#include "intel_reset.h"

#include "intel_ring.h"

drivers/gpu/drm/i915/gt/intel_gt_irq.c

+1 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include "intel_breadcrumbs.h"

#include "intel_gt.h"

#include "intel_gt_irq.h"

#include "intel_lrc_reg.h"

#include "intel_uncore.h"

#include "intel_rps.h"

drivers/gpu/drm/i915/gt/intel_lrc.h

+0 −39
Original line number Diff line number Diff line
@@ -34,45 +34,6 @@ struct i915_request; 
struct intel_context;

struct intel_engine_cs;



/* Execlists regs */

#define RING_ELSP(base)				_MMIO((base) + 0x230)

#define RING_EXECLIST_STATUS_LO(base)		_MMIO((base) + 0x234)

#define RING_EXECLIST_STATUS_HI(base)		_MMIO((base) + 0x234 + 4)

#define RING_CONTEXT_CONTROL(base)		_MMIO((base) + 0x244)

#define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	(1 << 3)

#define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)

#define   CTX_CTRL_RS_CTX_ENABLE		(1 << 1)

#define	  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT	(1 << 2)

#define	  GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE	(1 << 8)

#define RING_CONTEXT_STATUS_PTR(base)		_MMIO((base) + 0x3a0)

#define RING_EXECLIST_SQ_CONTENTS(base)		_MMIO((base) + 0x510)

#define RING_EXECLIST_CONTROL(base)		_MMIO((base) + 0x550)



#define	  EL_CTRL_LOAD				(1 << 0)



/* The docs specify that the write pointer wraps around after 5h, "After status

 * is written out to the last available status QW at offset 5h, this pointer

 * wraps to 0."

 *

 * Therefore, one must infer than even though there are 3 bits available, 6 and

 * 7 appear to be * reserved.

 */

#define GEN8_CSB_ENTRIES 6

#define GEN8_CSB_PTR_MASK 0x7

#define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)

#define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)



#define GEN11_CSB_ENTRIES 12

#define GEN11_CSB_PTR_MASK 0xf

#define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8)

#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)



#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */

#define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */

#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */

/* in Gen12 ID 0x7FF is reserved to indicate idle */

#define GEN12_MAX_CONTEXT_HW_ID	(GEN11_MAX_CONTEXT_HW_ID - 1)



enum {

	INTEL_CONTEXT_SCHEDULE_IN = 0,

	INTEL_CONTEXT_SCHEDULE_OUT,

drivers/gpu/drm/i915/gt/intel_lrc_reg.h

+39 −0
Original line number Diff line number Diff line
@@ -52,4 +52,43 @@ 
#define GEN8_EXECLISTS_STATUS_BUF 0x370

#define GEN11_EXECLISTS_STATUS_BUF2 0x3c0



/* Execlists regs */

#define RING_ELSP(base)				_MMIO((base) + 0x230)

#define RING_EXECLIST_STATUS_LO(base)		_MMIO((base) + 0x234)

#define RING_EXECLIST_STATUS_HI(base)		_MMIO((base) + 0x234 + 4)

#define RING_CONTEXT_CONTROL(base)		_MMIO((base) + 0x244)

#define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	REG_BIT(0)

#define   CTX_CTRL_RS_CTX_ENABLE		REG_BIT(1)

#define	  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT	REG_BIT(2)

#define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	REG_BIT(3)

#define	  GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE	REG_BIT(8)

#define RING_CONTEXT_STATUS_PTR(base)		_MMIO((base) + 0x3a0)

#define RING_EXECLIST_SQ_CONTENTS(base)		_MMIO((base) + 0x510)

#define RING_EXECLIST_CONTROL(base)		_MMIO((base) + 0x550)

#define	  EL_CTRL_LOAD				REG_BIT(0)



/*

 * The docs specify that the write pointer wraps around after 5h, "After status

 * is written out to the last available status QW at offset 5h, this pointer

 * wraps to 0."

 *

 * Therefore, one must infer than even though there are 3 bits available, 6 and

 * 7 appear to be * reserved.

 */

#define GEN8_CSB_ENTRIES 6

#define GEN8_CSB_PTR_MASK 0x7

#define GEN8_CSB_READ_PTR_MASK	(GEN8_CSB_PTR_MASK << 8)

#define GEN8_CSB_WRITE_PTR_MASK	(GEN8_CSB_PTR_MASK << 0)



#define GEN11_CSB_ENTRIES 12

#define GEN11_CSB_PTR_MASK 0xf

#define GEN11_CSB_READ_PTR_MASK		(GEN11_CSB_PTR_MASK << 8)

#define GEN11_CSB_WRITE_PTR_MASK	(GEN11_CSB_PTR_MASK << 0)



#define MAX_CONTEXT_HW_ID	(1 << 21) /* exclusive */

#define MAX_GUC_CONTEXT_HW_ID	(1 << 20) /* exclusive */

#define GEN11_MAX_CONTEXT_HW_ID	(1 << 11) /* exclusive */

/* in Gen12 ID 0x7FF is reserved to indicate idle */

#define GEN12_MAX_CONTEXT_HW_ID	(GEN11_MAX_CONTEXT_HW_ID - 1)



#endif /* _INTEL_LRC_REG_H_ */

drivers/gpu/drm/i915/gvt/mmio_context.h

+2 −0
Original line number Diff line number Diff line
@@ -36,6 +36,8 @@ 
#ifndef __GVT_RENDER_H__

#define __GVT_RENDER_H__



#include "gt/intel_lrc_reg.h"



struct engine_mmio {

	enum intel_engine_id id;

	i915_reg_t reg;