Loading arch/arm/boot/dts/dra7-l4.dtsi +1 −2 Original line number Diff line number Diff line Loading @@ -186,7 +186,6 @@ target-module@56000 { /* 0x4a056000, ap 9 02.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "dma_system"; reg = <0x56000 0x4>, <0x5602c 0x4>, <0x56028 0x4>; Loading @@ -212,7 +211,7 @@ ranges = <0x0 0x56000 0x1000>; sdma: dma-controller@0 { compatible = "ti,omap4430-sdma"; compatible = "ti,omap4430-sdma", "ti,omap-sdma"; reg = <0x0 0x1000>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, Loading arch/arm/boot/dts/omap2.dtsi +32 −11 Original line number Diff line number Diff line Loading @@ -8,6 +8,7 @@ * kind, whether express or implied. */ #include <dt-bindings/bus/ti-sysc.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/omap.h> Loading Loading @@ -79,10 +80,29 @@ reg = <0x480FE000 0x1000>; }; sdma: dma-controller@48056000 { compatible = "ti,omap2430-sdma", "ti,omap2420-sdma"; ti,hwmods = "dma"; reg = <0x48056000 0x1000>; target-module@48056000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x48056000 0x4>, <0x4805602c 0x4>, <0x48056028 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-midle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; ti,syss-mask = <1>; clocks = <&core_l3_ck>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x48056000 0x1000>; sdma: dma-controller@0 { compatible = "ti,omap2420-sdma", "ti,omap-sdma"; reg = <0 0x1000>; interrupts = <12>, <13>, <14>, Loading @@ -91,6 +111,7 @@ dma-channels = <32>; dma-requests = <64>; }; }; i2c1: i2c@48070000 { compatible = "ti,omap2-i2c"; Loading arch/arm/boot/dts/omap2430.dtsi +4 −0 Original line number Diff line number Diff line Loading @@ -309,6 +309,10 @@ }; }; &sdma { compatible = "ti,omap2430-sdma", "ti,omap-sdma"; }; &i2c1 { compatible = "ti,omap2430-i2c"; }; Loading arch/arm/boot/dts/omap3-n900.dts +5 −0 Original line number Diff line number Diff line Loading @@ -482,6 +482,11 @@ regulator-always-on; }; /* First two dma channels are reserved on secure omap3 */ &sdma { dma-channel-mask = <0xfffffffc>; }; &twl { twl_audio: audio { compatible = "ti,twl4030-audio"; Loading arch/arm/boot/dts/omap3.dtsi +35 −11 Original line number Diff line number Diff line Loading @@ -206,9 +206,33 @@ reg = <0x48200000 0x1000>; }; sdma: dma-controller@48056000 { compatible = "ti,omap3630-sdma", "ti,omap3430-sdma"; reg = <0x48056000 0x1000>; target-module@48056000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x48056000 0x4>, <0x4805602c 0x4>, <0x48056028 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-midle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */ clocks = <&core_l3_ick>; clock-names = "ick"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x48056000 0x1000>; sdma: dma-controller@0 { compatible = "ti,omap3430-sdma", "ti,omap-sdma"; reg = <0x0 0x1000>; interrupts = <12>, <13>, <14>, Loading @@ -216,7 +240,7 @@ #dma-cells = <1>; dma-channels = <32>; dma-requests = <96>; ti,hwmods = "dma"; }; }; gpio1: gpio@48310000 { Loading Loading
arch/arm/boot/dts/dra7-l4.dtsi +1 −2 Original line number Diff line number Diff line Loading @@ -186,7 +186,6 @@ target-module@56000 { /* 0x4a056000, ap 9 02.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "dma_system"; reg = <0x56000 0x4>, <0x5602c 0x4>, <0x56028 0x4>; Loading @@ -212,7 +211,7 @@ ranges = <0x0 0x56000 0x1000>; sdma: dma-controller@0 { compatible = "ti,omap4430-sdma"; compatible = "ti,omap4430-sdma", "ti,omap-sdma"; reg = <0x0 0x1000>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, Loading
arch/arm/boot/dts/omap2.dtsi +32 −11 Original line number Diff line number Diff line Loading @@ -8,6 +8,7 @@ * kind, whether express or implied. */ #include <dt-bindings/bus/ti-sysc.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/omap.h> Loading Loading @@ -79,10 +80,29 @@ reg = <0x480FE000 0x1000>; }; sdma: dma-controller@48056000 { compatible = "ti,omap2430-sdma", "ti,omap2420-sdma"; ti,hwmods = "dma"; reg = <0x48056000 0x1000>; target-module@48056000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x48056000 0x4>, <0x4805602c 0x4>, <0x48056028 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-midle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; ti,syss-mask = <1>; clocks = <&core_l3_ck>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x48056000 0x1000>; sdma: dma-controller@0 { compatible = "ti,omap2420-sdma", "ti,omap-sdma"; reg = <0 0x1000>; interrupts = <12>, <13>, <14>, Loading @@ -91,6 +111,7 @@ dma-channels = <32>; dma-requests = <64>; }; }; i2c1: i2c@48070000 { compatible = "ti,omap2-i2c"; Loading
arch/arm/boot/dts/omap2430.dtsi +4 −0 Original line number Diff line number Diff line Loading @@ -309,6 +309,10 @@ }; }; &sdma { compatible = "ti,omap2430-sdma", "ti,omap-sdma"; }; &i2c1 { compatible = "ti,omap2430-i2c"; }; Loading
arch/arm/boot/dts/omap3-n900.dts +5 −0 Original line number Diff line number Diff line Loading @@ -482,6 +482,11 @@ regulator-always-on; }; /* First two dma channels are reserved on secure omap3 */ &sdma { dma-channel-mask = <0xfffffffc>; }; &twl { twl_audio: audio { compatible = "ti,twl4030-audio"; Loading
arch/arm/boot/dts/omap3.dtsi +35 −11 Original line number Diff line number Diff line Loading @@ -206,9 +206,33 @@ reg = <0x48200000 0x1000>; }; sdma: dma-controller@48056000 { compatible = "ti,omap3630-sdma", "ti,omap3430-sdma"; reg = <0x48056000 0x1000>; target-module@48056000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x48056000 0x4>, <0x4805602c 0x4>, <0x48056028 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,sysc-midle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; ti,syss-mask = <1>; /* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */ clocks = <&core_l3_ick>; clock-names = "ick"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x48056000 0x1000>; sdma: dma-controller@0 { compatible = "ti,omap3430-sdma", "ti,omap-sdma"; reg = <0x0 0x1000>; interrupts = <12>, <13>, <14>, Loading @@ -216,7 +240,7 @@ #dma-cells = <1>; dma-channels = <32>; dma-requests = <96>; ti,hwmods = "dma"; }; }; gpio1: gpio@48310000 { Loading