dt-bindings: soc: socionext: Add UniPhier peripheral block

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-perictrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Socionext UniPhier peripheral block controller

maintainers:

  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

description: |+

  Peripheral block implemented on Socionext UniPhier SoCs is an integrated

  component of the peripherals including UART, I2C/FI2C, and SCSSI.

  Peripheral block controller is a logic to control the component.

properties:

  compatible:

    items:

      - enum:

          - socionext,uniphier-ld4-perictrl

          - socionext,uniphier-pro4-perictrl

          - socionext,uniphier-pro5-perictrl

          - socionext,uniphier-pxs2-perictrl

          - socionext,uniphier-sld8-perictrl

          - socionext,uniphier-ld11-perictrl

          - socionext,uniphier-ld20-perictrl

          - socionext,uniphier-pxs3-perictrl

          - socionext,uniphier-nx1-perictrl

      - const: simple-mfd

      - const: syscon

  reg:

    maxItems: 1

  clock-controller:

    $ref: /schemas/clock/socionext,uniphier-clock.yaml#

  reset-controller:

    $ref: /schemas/reset/socionext,uniphier-reset.yaml#

required:

  - compatible

  - reg

additionalProperties: false

examples:

  - |

    syscon@59820000 {

        compatible = "socionext,uniphier-ld20-perictrl",

                     "simple-mfd", "syscon";

        reg = <0x59820000 0x200>;

        clock-controller {

            compatible = "socionext,uniphier-ld20-peri-clock";

            #clock-cells = <1>;

        };

        reset-controller {

            compatible = "socionext,uniphier-ld20-peri-reset";

            #reset-cells = <1>;

        };

    };