Commit 9fac2a19 authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Miquel Raynal
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dt-bindings: mtd: intel: lgm-nand: Fix maximum chip select value 



The Intel LGM NAND IP only supports two chip selects: There's only two
CS and ADDR_SEL register sets. Fix the maximum allowed chip select value
according to the dt-bindings.

Fixes: 2f9cea8e ("dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC")
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20220702231227.1579176-3-martin.blumenstingl@googlemail.com
parent c6d7ce0a

Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml

+1 −1
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ patternProperties: 
    properties:

      reg:

        minimum: 0

        maximum: 7

        maximum: 1



      nand-ecc-mode: true