Commit 9f95e778 authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Adjust types and formatting for future development 



Type adjustments and formatting fixes.

Signed-off-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cf83f5cf

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

+6 −5
Original line number Diff line number Diff line
@@ -2267,7 +2267,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman 
					&locals->UrgentBurstFactorLumaPre[k],

					&locals->UrgentBurstFactorChroma[k],

					&locals->UrgentBurstFactorChromaPre[k],

					&locals->NotEnoughUrgentLatencyHiding,

					&locals->NotEnoughUrgentLatencyHiding[0][0],

					&locals->NotEnoughUrgentLatencyHidingPre);



			if (mode_lib->vba.UseUrgentBurstBandwidth == false) {
@@ -2300,7 +2300,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman 
		}

		mode_lib->vba.FractionOfUrgentBandwidth = MaxTotalRDBandwidthNoUrgentBurst / mode_lib->vba.ReturnBW;



		if (MaxTotalRDBandwidth <= mode_lib->vba.ReturnBW && locals->NotEnoughUrgentLatencyHiding == 0 && locals->NotEnoughUrgentLatencyHidingPre == 0 && !VRatioPrefetchMoreThan4

		if (MaxTotalRDBandwidth <= mode_lib->vba.ReturnBW && locals->NotEnoughUrgentLatencyHiding[0][0] == 0 &&

				locals->NotEnoughUrgentLatencyHidingPre == 0 && !VRatioPrefetchMoreThan4

				&& !DestinationLineTimesForPrefetchLessThan2)

			mode_lib->vba.PrefetchModeSupported = true;

		else {
@@ -4821,7 +4822,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
							&locals->UrgentBurstFactorLumaPre[k],

							&locals->UrgentBurstFactorChroma[k],

							&locals->UrgentBurstFactorChromaPre[k],

							&locals->NotEnoughUrgentLatencyHiding,

							&locals->NotEnoughUrgentLatencyHiding[0][0],

							&locals->NotEnoughUrgentLatencyHidingPre);



					if (mode_lib->vba.UseUrgentBurstBandwidth == false) {
@@ -4848,13 +4849,13 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
				}

				locals->BandwidthWithoutPrefetchSupported[i][0] = true;

				if (mode_lib->vba.MaximumReadBandwidthWithoutPrefetch > locals->ReturnBWPerState[i][0]

						|| locals->NotEnoughUrgentLatencyHiding == 1) {

						|| locals->NotEnoughUrgentLatencyHiding[0][0] == 1) {

					locals->BandwidthWithoutPrefetchSupported[i][0] = false;

				}



				locals->PrefetchSupported[i][j] = true;

				if (mode_lib->vba.MaximumReadBandwidthWithPrefetch > locals->ReturnBWPerState[i][0]

						|| locals->NotEnoughUrgentLatencyHiding == 1

						|| locals->NotEnoughUrgentLatencyHiding[0][0] == 1

						|| locals->NotEnoughUrgentLatencyHidingPre == 1) {

					locals->PrefetchSupported[i][j] = false;

				}

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

+10 −8
Original line number Diff line number Diff line
@@ -2596,7 +2596,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman 
			}

		}



		v->NotEnoughUrgentLatencyHiding = false;

		v->NotEnoughUrgentLatencyHiding[0][0] = false;

		v->NotEnoughUrgentLatencyHidingPre = false;



		for (k = 0; k < v->NumberOfActivePlanes; ++k) {
@@ -2681,7 +2681,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman 
			if (v->VRatioPrefetchY[k] > 4 || v->VRatioPrefetchC[k] > 4)

				VRatioPrefetchMoreThan4 = true;

			if (v->NoUrgentLatencyHiding[k] == true)

				v->NotEnoughUrgentLatencyHiding = true;

				v->NotEnoughUrgentLatencyHiding[0][0] = true;



			if (v->NoUrgentLatencyHidingPre[k] == true)

				v->NotEnoughUrgentLatencyHidingPre = true;
@@ -2689,7 +2689,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman 
		v->FractionOfUrgentBandwidth = MaxTotalRDBandwidthNoUrgentBurst / v->ReturnBW;





		if (MaxTotalRDBandwidth <= v->ReturnBW && v->NotEnoughUrgentLatencyHiding == 0 && v->NotEnoughUrgentLatencyHidingPre == 0 && !VRatioPrefetchMoreThan4

		if (MaxTotalRDBandwidth <= v->ReturnBW && v->NotEnoughUrgentLatencyHiding[0][0] == 0

				&& v->NotEnoughUrgentLatencyHidingPre == 0 && !VRatioPrefetchMoreThan4

				&& !DestinationLineTimesForPrefetchLessThan2)

			v->PrefetchModeSupported = true;

		else {
@@ -2794,8 +2795,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman 
		}



		v->VStartupLines = v->VStartupLines + 1;

		v->PrefetchAndImmediateFlipSupported = (v->PrefetchModeSupported == true && ((!v->ImmediateFlipSupport && !v->HostVMEnable && v->ImmediateFlipRequirement != dm_immediate_flip_required) || v->ImmediateFlipSupported)) ? true : false;



		v->PrefetchModeSupported = (v->PrefetchModeSupported == true && ((!v->ImmediateFlipSupport &&

				!v->HostVMEnable && v->ImmediateFlipRequirement[0] != dm_immediate_flip_required) ||

				v->ImmediateFlipSupported)) ? true : false;

	} while (!v->PrefetchModeSupported && v->VStartupLines <= v->MaximumMaxVStartupLines);

	ASSERT(v->PrefetchModeSupported);
@@ -4753,7 +4755,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
				v->HostVMMinPageSize,

				v->HostVMMaxNonCachedPageTableLevels,

				v->DynamicMetadataVMEnabled,

				v->ImmediateFlipRequirement,

				v->ImmediateFlipRequirement[0],

				v->ProgressiveToInterlaceUnitInOPP,

				v->MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation,

				v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
@@ -5164,7 +5166,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
					v->NextMaxVStartup = v->NextMaxVStartup - 1;

				}

			} while (!((v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true

					&& ((v->HostVMEnable == false && v->ImmediateFlipRequirement != dm_immediate_flip_required)

					&& ((v->HostVMEnable == false && v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)

							|| v->ImmediateFlipSupportedForState[i][j] == true))

					|| (v->NextMaxVStartup == v->MaxMaxVStartup[i][j] && NextPrefetchModeState > MaxPrefetchMode)));
@@ -5305,7 +5307,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
					&& ViewportExceedsSurface == 0 && v->PrefetchSupported[i][j] == 1 && v->DynamicMetadataSupported[i][j] == 1

					&& v->TotalVerticalActiveBandwidthSupport[i][j] == 1 && v->VRatioInPrefetchSupported[i][j] == 1

					&& v->PTEBufferSizeNotExceeded[i][j] == 1 && v->NonsupportedDSCInputBPC == 0

					&& ((v->HostVMEnable == 0 && v->ImmediateFlipRequirement != dm_immediate_flip_required)

					&& ((v->HostVMEnable == 0 && v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)

							|| v->ImmediateFlipSupportedForState[i][j] == true)) {

				v->ModeSupport[i][j] = true;

			} else {

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

+8 −7
Original line number Diff line number Diff line
@@ -3036,10 +3036,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman 
		}



		v->PrefetchAndImmediateFlipSupported =

				(v->PrefetchModeSupported == true

						&& ((!v->ImmediateFlipSupport && !v->HostVMEnable

								&& v->ImmediateFlipRequirement != dm_immediate_flip_required) || v->ImmediateFlipSupported)) ?

						true : false;

				(v->PrefetchModeSupported == true && ((!v->ImmediateFlipSupport && !v->HostVMEnable

				&& v->ImmediateFlipRequirement[0] != dm_immediate_flip_required) ||

				v->ImmediateFlipSupported)) ? true : false;

#ifdef __DML_VBA_DEBUG__

		dml_print("DML::%s: PrefetchModeSupported %d\n", __func__, v->PrefetchModeSupported);

		dml_print("DML::%s: ImmediateFlipRequirement %d\n", __func__, v->ImmediateFlipRequirement == dm_immediate_flip_required);
@@ -5103,7 +5102,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
				v->HostVMMinPageSize,

				v->HostVMMaxNonCachedPageTableLevels,

				v->DynamicMetadataVMEnabled,

				v->ImmediateFlipRequirement,

				v->ImmediateFlipRequirement[0],

				v->ProgressiveToInterlaceUnitInOPP,

				v->MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation,

				v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency,
@@ -5542,7 +5541,8 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
				}

				v->NextPrefetchMode = v->NextPrefetchMode + 1;

			} while (!((v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true

					&& ((v->HostVMEnable == false && v->ImmediateFlipRequirement != dm_immediate_flip_required)

					&& ((v->HostVMEnable == false &&

							v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)

							|| v->ImmediateFlipSupportedForState[i][j] == true))

					|| (v->NextMaxVStartup == v->MaxMaxVStartup[i][j] && NextPrefetchModeState > MaxPrefetchMode)));
@@ -5702,7 +5702,8 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
					&& v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true

					&& v->TotalVerticalActiveBandwidthSupport[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true

					&& v->PTEBufferSizeNotExceeded[i][j] == true && v->NonsupportedDSCInputBPC == false

					&& ((v->HostVMEnable == false && v->ImmediateFlipRequirement != dm_immediate_flip_required)

					&& ((v->HostVMEnable == false

					&& v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)

							|| v->ImmediateFlipSupportedForState[i][j] == true)

					&& FMTBufferExceeded == false) {

				v->ModeSupport[i][j] = true;

drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h

+3 −1
Original line number Diff line number Diff line
@@ -109,7 +109,9 @@ enum clock_change_support { 
};



enum output_standard {

	dm_std_uninitialized = 0, dm_std_cvtr2, dm_std_cvt

	dm_std_uninitialized = 0,

	dm_std_cvtr2,

	dm_std_cvt

};



enum mpc_combine_affinity {

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c

+7 −5
Original line number Diff line number Diff line
@@ -396,7 +396,6 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) 


	mode_lib->vba.NumberOfActivePlanes = 0;

	mode_lib->vba.ImmediateFlipSupport = false;

	mode_lib->vba.ImmediateFlipRequirement = dm_immediate_flip_not_required;

	for (j = 0; j < mode_lib->vba.cache_num_pipes; ++j) {

		display_pipe_source_params_st *src = &pipes[j].pipe.src;

		display_pipe_dest_params_st *dst = &pipes[j].pipe.dest;
@@ -409,6 +408,7 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) 
			continue;

		visited[j] = true;



		mode_lib->vba.ImmediateFlipRequirement[j] = dm_immediate_flip_not_required;

		mode_lib->vba.pipe_plane[j] = mode_lib->vba.NumberOfActivePlanes;

		mode_lib->vba.DPPPerPlane[mode_lib->vba.NumberOfActivePlanes] = 1;

		mode_lib->vba.SourceScan[mode_lib->vba.NumberOfActivePlanes] =
@@ -667,9 +667,9 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) 
				mode_lib->vba.ViewportHeightChroma[mode_lib->vba.NumberOfActivePlanes] = src->viewport_height_max / vdiv_c;

		}



		if (pipes[k].pipe.src.immediate_flip) {

		if (pipes[j].pipe.src.immediate_flip) {

			mode_lib->vba.ImmediateFlipSupport = true;

			mode_lib->vba.ImmediateFlipRequirement = dm_immediate_flip_required;

			mode_lib->vba.ImmediateFlipRequirement[j] = dm_immediate_flip_required;

		}



		mode_lib->vba.NumberOfActivePlanes++;
@@ -845,9 +845,10 @@ void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib * 


	//Progressive To Interlace Unit Effect

	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {

		mode_lib->vba.PixelClockBackEnd[k] = mode_lib->vba.PixelClock[k];

		if (mode_lib->vba.Interlace[k] == 1

				&& mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true) {

			mode_lib->vba.PixelClock[k] = 2 * mode_lib->vba.PixelClockBackEnd[k];

			mode_lib->vba.PixelClock[k] = 2 * mode_lib->vba.PixelClock[k];

		}

	}

}
@@ -890,8 +891,9 @@ void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib) 
		mode_lib->vba.DISPCLK = soc->clock_limits[mode_lib->vba.VoltageLevel].dispclk_mhz;



	// Total Available Pipes Support Check

	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)

	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {

		total_pipes += mode_lib->vba.DPPPerPlane[k];

	}

	ASSERT(total_pipes <= DC__NUM_DPP__MAX);

}