Commit 9f794a8b authored by Qi Liu's avatar Qi Liu Committed by Zheng Zengkai
Browse files

perf auxtrace arm64: Add support for parsing HiSilicon PCIe Trace packet 

mainline inclusion
from mainline-v6.1-rc1
commit 5e91e57e
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I5WGEF
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5e91e57e6809



--------------------------------------------------------------------------

Add support for using 'perf report --dump-raw-trace' to parse PTT packet.

Example usage:

Output will contain raw PTT data and its textual representation, such
as (8DW format):

0 0 0x5810 [0x30]: PERF_RECORD_AUXTRACE size: 0x400000  offset: 0
ref: 0xa5d50c725  idx: 0  tid: -1  cpu: 0
.
. ... HISI PTT data: size 4194304 bytes
.  00000000: 00 00 00 00                                 Prefix
.  00000004: 08 20 00 60                                 Header DW0
.  00000008: ff 02 00 01                                 Header DW1
.  0000000c: 20 08 00 00                                 Header DW2
.  00000010: 10 e7 44 ab                                 Header DW3
.  00000014: 2a a8 1e 01                                 Time
.  00000020: 00 00 00 00                                 Prefix
.  00000024: 01 00 00 60                                 Header DW0
.  00000028: 0f 1e 00 01                                 Header DW1
.  0000002c: 04 00 00 00                                 Header DW2
.  00000030: 40 00 81 02                                 Header DW3
.  00000034: ee 02 00 00                                 Time
....

This patch only add basic parsing support according to the definition of
the PTT packet described in Documentation/trace/hisi-ptt.rst. And the
fields of each packet can be further decoded following the PCIe Spec's
definition of TLP packet.

Signed-off-by: default avatarQi Liu <liuqi115@huawei.com>
Signed-off-by: default avatarYicong Yang <yangyicong@hisilicon.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Bjorn Helgaas <helgaas@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: John Garry <john.garry@huawei.com>
Cc: Jonathan Cameron <jonathan.cameron@huawei.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Qi Liu <liuqi6124@gmail.com>
Cc: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Suzuki Poulouse <suzuki.poulose@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Zeng Prime <prime.zeng@huawei.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-pci@vger.kernel.org
Cc: linuxarm@huawei.com
Link: https://lore.kernel.org/r/20220927081400.14364-4-yangyicong@huawei.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: default avatarWangming Shao <shaowangming@h-partners.com>
Reviewed-by: default avatarYang Jihong <yangjihong1@huawei.com>
Reviewed-by: default avatarJay Fang <f.fangjian@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent 83e1a377

tools/perf/util/Build

+2 −0
Original line number Diff line number Diff line
@@ -109,6 +109,8 @@ perf-$(CONFIG_AUXTRACE) += intel-pt.o 
perf-$(CONFIG_AUXTRACE) += intel-bts.o

perf-$(CONFIG_AUXTRACE) += arm-spe.o

perf-$(CONFIG_AUXTRACE) += arm-spe-decoder/

perf-$(CONFIG_AUXTRACE) += hisi-ptt.o

perf-$(CONFIG_AUXTRACE) += hisi-ptt-decoder/

perf-$(CONFIG_AUXTRACE) += s390-cpumsf.o



ifdef CONFIG_LIBOPENCSD

tools/perf/util/auxtrace.c

+3 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ 
#include "intel-pt.h"

#include "intel-bts.h"

#include "arm-spe.h"

#include "hisi-ptt.h"

#include "s390-cpumsf.h"

#include "util/mmap.h"
@@ -1274,6 +1275,8 @@ int perf_event__process_auxtrace_info(struct perf_session *session, 
		err = s390_cpumsf_process_auxtrace_info(event, session);

		break;

	case PERF_AUXTRACE_HISI_PTT:

		err = hisi_ptt_process_auxtrace_info(event, session);

		break;

	case PERF_AUXTRACE_UNKNOWN:

	default:

		return -EINVAL;

tools/perf/util/hisi-ptt-decoder/Build

0 → 100644
+1 −0
Original line number Diff line number Diff line 
perf-$(CONFIG_AUXTRACE) += hisi-ptt-pkt-decoder.o

tools/perf/util/hisi-ptt-decoder/hisi-ptt-pkt-decoder.c

0 → 100644
+164 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * HiSilicon PCIe Trace and Tuning (PTT) support

 * Copyright (c) 2022 HiSilicon Technologies Co., Ltd.

 */



#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <endian.h>

#include <byteswap.h>

#include <linux/bitops.h>

#include <stdarg.h>



#include "../color.h"

#include "hisi-ptt-pkt-decoder.h"



/*

 * For 8DW format, the bit[31:11] of DW0 is always 0x1fffff, which can be

 * used to distinguish the data format.

 * 8DW format is like:

 *   bits [                 31:11                 ][       10:0       ]

 *        |---------------------------------------|-------------------|

 *    DW0 [                0x1fffff               ][ Reserved (0x7ff) ]

 *    DW1 [                       Prefix                              ]

 *    DW2 [                     Header DW0                            ]

 *    DW3 [                     Header DW1                            ]

 *    DW4 [                     Header DW2                            ]

 *    DW5 [                     Header DW3                            ]

 *    DW6 [                   Reserved (0x0)                          ]

 *    DW7 [                        Time                               ]

 *

 * 4DW format is like:

 *   bits [31:30] [ 29:25 ][24][23][22][21][    20:11   ][    10:0    ]

 *        |-----|---------|---|---|---|---|-------------|-------------|

 *    DW0 [ Fmt ][  Type  ][T9][T8][TH][SO][   Length   ][    Time    ]

 *    DW1 [                     Header DW1                            ]

 *    DW2 [                     Header DW2                            ]

 *    DW3 [                     Header DW3                            ]

 */



enum hisi_ptt_8dw_pkt_field_type {

	HISI_PTT_8DW_CHK_AND_RSV0,

	HISI_PTT_8DW_PREFIX,

	HISI_PTT_8DW_HEAD0,

	HISI_PTT_8DW_HEAD1,

	HISI_PTT_8DW_HEAD2,

	HISI_PTT_8DW_HEAD3,

	HISI_PTT_8DW_RSV1,

	HISI_PTT_8DW_TIME,

	HISI_PTT_8DW_TYPE_MAX

};



enum hisi_ptt_4dw_pkt_field_type {

	HISI_PTT_4DW_HEAD1,

	HISI_PTT_4DW_HEAD2,

	HISI_PTT_4DW_HEAD3,

	HISI_PTT_4DW_TYPE_MAX

};



static const char * const hisi_ptt_8dw_pkt_field_name[] = {

	[HISI_PTT_8DW_PREFIX]	= "Prefix",

	[HISI_PTT_8DW_HEAD0]	= "Header DW0",

	[HISI_PTT_8DW_HEAD1]	= "Header DW1",

	[HISI_PTT_8DW_HEAD2]	= "Header DW2",

	[HISI_PTT_8DW_HEAD3]	= "Header DW3",

	[HISI_PTT_8DW_TIME]	= "Time"

};



static const char * const hisi_ptt_4dw_pkt_field_name[] = {

	[HISI_PTT_4DW_HEAD1]	= "Header DW1",

	[HISI_PTT_4DW_HEAD2]	= "Header DW2",

	[HISI_PTT_4DW_HEAD3]	= "Header DW3",

};



union hisi_ptt_4dw {

	struct {

		uint32_t format : 2;

		uint32_t type : 5;

		uint32_t t9 : 1;

		uint32_t t8 : 1;

		uint32_t th : 1;

		uint32_t so : 1;

		uint32_t len : 10;

		uint32_t time : 11;

	};

	uint32_t value;

};



static void hisi_ptt_print_pkt(const unsigned char *buf, int pos, const char *desc)

{

	const char *color = PERF_COLOR_BLUE;

	int i;



	printf(".");

	color_fprintf(stdout, color, "  %08x: ", pos);

	for (i = 0; i < HISI_PTT_FIELD_LENTH; i++)

		color_fprintf(stdout, color, "%02x ", buf[pos + i]);

	for (i = 0; i < HISI_PTT_MAX_SPACE_LEN; i++)

		color_fprintf(stdout, color, "   ");

	color_fprintf(stdout, color, "  %s\n", desc);

}



static int hisi_ptt_8dw_kpt_desc(const unsigned char *buf, int pos)

{

	int i;



	for (i = 0; i < HISI_PTT_8DW_TYPE_MAX; i++) {

		/* Do not show 8DW check field and reserved fields */

		if (i == HISI_PTT_8DW_CHK_AND_RSV0 || i == HISI_PTT_8DW_RSV1) {

			pos += HISI_PTT_FIELD_LENTH;

			continue;

		}



		hisi_ptt_print_pkt(buf, pos, hisi_ptt_8dw_pkt_field_name[i]);

		pos += HISI_PTT_FIELD_LENTH;

	}



	return hisi_ptt_pkt_size[HISI_PTT_8DW_PKT];

}



static void hisi_ptt_4dw_print_dw0(const unsigned char *buf, int pos)

{

	const char *color = PERF_COLOR_BLUE;

	union hisi_ptt_4dw dw0;

	int i;



	dw0.value = *(uint32_t *)(buf + pos);

	printf(".");

	color_fprintf(stdout, color, "  %08x: ", pos);

	for (i = 0; i < HISI_PTT_FIELD_LENTH; i++)

		color_fprintf(stdout, color, "%02x ", buf[pos + i]);

	for (i = 0; i < HISI_PTT_MAX_SPACE_LEN; i++)

		color_fprintf(stdout, color, "   ");



	color_fprintf(stdout, color,

		      "  %s %x %s %x %s %x %s %x %s %x %s %x %s %x %s %x\n",

		      "Format", dw0.format, "Type", dw0.type, "T9", dw0.t9,

		      "T8", dw0.t8, "TH", dw0.th, "SO", dw0.so, "Length",

		      dw0.len, "Time", dw0.time);

}



static int hisi_ptt_4dw_kpt_desc(const unsigned char *buf, int pos)

{

	int i;



	hisi_ptt_4dw_print_dw0(buf, pos);

	pos += HISI_PTT_FIELD_LENTH;



	for (i = 0; i < HISI_PTT_4DW_TYPE_MAX; i++) {

		hisi_ptt_print_pkt(buf, pos, hisi_ptt_4dw_pkt_field_name[i]);

		pos += HISI_PTT_FIELD_LENTH;

	}



	return hisi_ptt_pkt_size[HISI_PTT_4DW_PKT];

}



int hisi_ptt_pkt_desc(const unsigned char *buf, int pos, enum hisi_ptt_pkt_type type)

{

	if (type == HISI_PTT_8DW_PKT)

		return hisi_ptt_8dw_kpt_desc(buf, pos);



	return hisi_ptt_4dw_kpt_desc(buf, pos);

}

tools/perf/util/hisi-ptt-decoder/hisi-ptt-pkt-decoder.h

0 → 100644
+31 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * HiSilicon PCIe Trace and Tuning (PTT) support

 * Copyright (c) 2022 HiSilicon Technologies Co., Ltd.

 */



#ifndef INCLUDE__HISI_PTT_PKT_DECODER_H__

#define INCLUDE__HISI_PTT_PKT_DECODER_H__



#include <stddef.h>

#include <stdint.h>



#define HISI_PTT_8DW_CHECK_MASK		GENMASK(31, 11)

#define HISI_PTT_IS_8DW_PKT		GENMASK(31, 11)

#define HISI_PTT_MAX_SPACE_LEN		10

#define HISI_PTT_FIELD_LENTH		4



enum hisi_ptt_pkt_type {

	HISI_PTT_4DW_PKT,

	HISI_PTT_8DW_PKT,

	HISI_PTT_PKT_MAX

};



static int hisi_ptt_pkt_size[] = {

	[HISI_PTT_4DW_PKT]	= 16,

	[HISI_PTT_8DW_PKT]	= 32,

};



int hisi_ptt_pkt_desc(const unsigned char *buf, int pos, enum hisi_ptt_pkt_type type);



#endif