Commit 9f74d770 authored by Tan Xiaojun's avatar Tan Xiaojun Committed by Arnaldo Carvalho de Melo
Browse files

perf auxtrace: Add four itrace options 



This patch is to add four options to synthesize events which are
described as below:

 'f': synthesize first level cache events
 'm': synthesize last level cache events
 't': synthesize TLB events
 'a': synthesize remote access events

This four options will be used by ARM SPE as their first consumer.

Signed-off-by: default avatarTan Xiaojun <tanxiaojun@huawei.com>
Tested-by: default avatarJames Clark <james.clark@arm.com>
Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Cc: Al Grant <al.grant@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Jin Yao <yao.jin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lore.kernel.org/lkml/20200530122442.490-3-leo.yan@linaro.org


Signed-off-by: default avatarJames Clark <james.clark@arm.com>
Signed-off-by: default avatarLeo Yan <leo.yan@linaro.org>
Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 4db25f66

tools/perf/Documentation/itrace.txt

+5 −1
Original line number Diff line number Diff line 
		i	synthesize instructions events

		b	synthesize branches events

		b	synthesize branches events (branch misses for Arm SPE)

		c	synthesize branches events (calls only)

		r	synthesize branches events (returns only)

		x	synthesize transactions events
@@ -9,6 +9,10 @@ 
			of aux-output (refer to perf record)

		e	synthesize error events

		d	create a debug log

		f	synthesize first level cache events

		m	synthesize last level cache events

		t	synthesize TLB events

		a	synthesize remote access events

		g	synthesize a call chain (use with i or x)

		G	synthesize a call chain on existing event records

		l	synthesize last branch entries (use with i or x)

tools/perf/util/auxtrace.c

+17 −0
Original line number Diff line number Diff line
@@ -1331,6 +1331,11 @@ void itrace_synth_opts__set_default(struct itrace_synth_opts *synth_opts, 
	synth_opts->pwr_events = true;

	synth_opts->other_events = true;

	synth_opts->errors = true;

	synth_opts->flc = true;

	synth_opts->llc = true;

	synth_opts->tlb = true;

	synth_opts->remote_access = true;



	if (no_sample) {

		synth_opts->period_type = PERF_ITRACE_PERIOD_INSTRUCTIONS;

		synth_opts->period = 1;
@@ -1491,6 +1496,18 @@ int itrace_parse_synth_opts(const struct option *opt, const char *str, 
				goto out_err;

			p = endptr;

			break;

		case 'f':

			synth_opts->flc = true;

			break;

		case 'm':

			synth_opts->llc = true;

			break;

		case 't':

			synth_opts->tlb = true;

			break;

		case 'a':

			synth_opts->remote_access = true;

			break;

		case ' ':

		case ',':

			break;

tools/perf/util/auxtrace.h

+14 −1
Original line number Diff line number Diff line
@@ -63,6 +63,7 @@ enum itrace_period_type { 
 *          because 'perf inject' will write it out

 * @instructions: whether to synthesize 'instructions' events

 * @branches: whether to synthesize 'branches' events

 *            (branch misses only for Arm SPE)

 * @transactions: whether to synthesize events for transactions

 * @ptwrites: whether to synthesize events for ptwrites

 * @pwr_events: whether to synthesize power events
@@ -78,6 +79,10 @@ enum itrace_period_type { 
 * @thread_stack: feed branches to the thread_stack

 * @last_branch: add branch context to 'instruction' events

 * @add_last_branch: add branch context to existing event records

 * @flc: whether to synthesize first level cache events

 * @llc: whether to synthesize last level cache events

 * @tlb: whether to synthesize TLB events

 * @remote_access: whether to synthesize remote access events

 * @callchain_sz: maximum callchain size

 * @last_branch_sz: branch context size

 * @period: 'instructions' events period
@@ -107,6 +112,10 @@ struct itrace_synth_opts { 
	bool			thread_stack;

	bool			last_branch;

	bool			add_last_branch;

	bool			flc;

	bool			llc;

	bool			tlb;

	bool			remote_access;

	unsigned int		callchain_sz;

	unsigned int		last_branch_sz;

	unsigned long long	period;
@@ -596,7 +605,7 @@ bool auxtrace__evsel_is_auxtrace(struct perf_session *session, 


#define ITRACE_HELP \

"				i:	    		synthesize instructions events\n"		\

"				b:	    		synthesize branches events\n"		\

"				b:	    		synthesize branches events (branch misses for Arm SPE)\n" \

"				c:	    		synthesize branches events (calls only)\n"	\

"				r:	    		synthesize branches events (returns only)\n" \

"				x:	    		synthesize transactions events\n"		\
@@ -604,6 +613,10 @@ bool auxtrace__evsel_is_auxtrace(struct perf_session *session, 
"				p:	    		synthesize power events\n"			\

"				e:	    		synthesize error events\n"			\

"				d:	    		create a debug log\n"			\

"				f:	    		synthesize first level cache events\n" \

"				m:	    		synthesize last level cache events\n" \

"				t:	    		synthesize TLB events\n" \

"				a:	    		synthesize remote access events\n" \

"				g[len]:     		synthesize a call chain (use with i or x)\n" \

"				l[len]:     		synthesize last branch entries (use with i or x)\n" \

"				sNUMBER:    		skip initial number of events\n"		\