Commit 9f6b3672 authored by Jijie Shao's avatar Jijie Shao Committed by Jiantao Xiao
Browse files

net: hns3: fix reset timeout when enable full VF 

mainlist inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I72OPH
CVE: NA

Reference: https://patchwork.kernel.org/project/netdevbpf/patch/20230512100014.2522-5-lanhao@huawei.com/



----------------------------------------------------------------------

The timeout of the cmdq reset command has been increased to
resolve the reset timeout issue in the full VF scenario.
The timeout of other cmdq commands remains unchanged.

Fixes: 8d307f8e ("net: hns3: create new set of unified hclge_comm_cmd_send APIs")
Signed-off-by: default avatarJijie Shao <shaojijie@huawei.com>
Signed-off-by: default avatarHao Lan <lanhao@huawei.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
Signed-off-by: default avatarJiantao Xiao <xiaojiantao1@h-partners.com>
parent 73361056

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c

+21 −4
Original line number Diff line number Diff line
@@ -332,9 +332,25 @@ static int hclge_comm_cmd_csq_done(struct hclge_comm_hw *hw) 
	return head == hw->cmq.csq.next_to_use;

}



static void hclge_comm_wait_for_resp(struct hclge_comm_hw *hw,

static u32 hclge_get_cmdq_tx_timeout(u16 opcode, u32 tx_timeout)

{

	static const struct hclge_cmdq_tx_timeout_map cmdq_tx_timeout_map[] = {

		{HCLGE_OPC_CFG_RST_TRIGGER, HCLGE_COMM_CMDQ_TX_TIMEOUT_500MS},

	};

	u32 i;



	for (i = 0; i < ARRAY_SIZE(cmdq_tx_timeout_map); i++)

		if (cmdq_tx_timeout_map[i].opcode == opcode)

			return cmdq_tx_timeout_map[i].tx_timeout;



	return tx_timeout;

}



static void hclge_comm_wait_for_resp(struct hclge_comm_hw *hw, u16 opcode,

				     bool *is_completed)

{

	u32 cmdq_tx_timeout = hclge_get_cmdq_tx_timeout(opcode,

							hw->cmq.tx_timeout);

	u32 timeout = 0;



	do {
@@ -344,7 +360,7 @@ static void hclge_comm_wait_for_resp(struct hclge_comm_hw *hw, 
		}

		udelay(1);

		timeout++;

	} while (timeout < hw->cmq.tx_timeout);

	} while (timeout < cmdq_tx_timeout);

}



static int hclge_comm_cmd_convert_err_code(u16 desc_ret)
@@ -408,7 +424,8 @@ static int hclge_comm_cmd_check_result(struct hclge_comm_hw *hw, 
	 * if multi descriptors to be sent, use the first one to check

	 */

	if (HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag)))

		hclge_comm_wait_for_resp(hw, &is_completed);

		hclge_comm_wait_for_resp(hw, le16_to_cpu(desc->opcode),

					 &is_completed);



	if (!is_completed)

		ret = -EBADE;
@@ -530,7 +547,7 @@ int hclge_comm_cmd_queue_init(struct pci_dev *pdev, struct hclge_comm_hw *hw) 
	cmdq->crq.desc_num = HCLGE_COMM_NIC_CMQ_DESC_NUM;



	/* Setup Tx write back timeout */

	cmdq->tx_timeout = HCLGE_COMM_CMDQ_TX_TIMEOUT;

	cmdq->tx_timeout = HCLGE_COMM_CMDQ_TX_TIMEOUT_DEFAULT;



	/* Setup queue rings */

	ret = hclge_comm_alloc_cmd_queue(hw, HCLGE_COMM_TYPE_CSQ);

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h

+7 −1
Original line number Diff line number Diff line
@@ -54,7 +54,8 @@ 
#define HCLGE_COMM_NIC_SW_RST_RDY		BIT(HCLGE_COMM_NIC_SW_RST_RDY_B)

#define HCLGE_COMM_NIC_CMQ_DESC_NUM_S		3

#define HCLGE_COMM_NIC_CMQ_DESC_NUM		1024

#define HCLGE_COMM_CMDQ_TX_TIMEOUT		30000

#define HCLGE_COMM_CMDQ_TX_TIMEOUT_DEFAULT	30000

#define HCLGE_COMM_CMDQ_TX_TIMEOUT_500MS	500000



enum hclge_opcode_type {

	/* Generic commands */
@@ -361,6 +362,11 @@ struct hclge_comm_caps_bit_map { 
	u16 local_bit;

};



struct hclge_cmdq_tx_timeout_map {

	u32 opcode;

	u32 tx_timeout;

};



struct hclge_comm_firmware_compat_cmd {

	__le32 compat;

	u8 rsv[20];