Commit 9f5171ce authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Add 16 lines margin for SubVP 



[Description]
SUBVP_START_LINE must be aligned to 2 swaths, so add
16 lines of margin so the start line can be adjusted by
up to 16 lines for alignment purposes in FW.

Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 30456ffa

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -213,6 +213,7 @@ struct dc_caps { 
	uint32_t cache_num_ways;

	uint16_t subvp_fw_processing_delay_us;

	uint16_t subvp_prefetch_end_to_mall_start_us;

	uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height

	uint16_t subvp_pstate_allow_width_us;

	uint16_t subvp_vertical_int_margin_us;

	bool seamless_odm;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

+2 −2
Original line number Diff line number Diff line
@@ -275,8 +275,7 @@ void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst) 
	union dmub_rb_cmd cmd = { 0 };



	cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;

	// TODO: Uncomment once FW headers are promoted

	//cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER;

	cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER;

	cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;



	cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);
@@ -612,6 +611,7 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc, 
			main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable;

	pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable;

	pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->pipe_idx;

	pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param;



	// Prefetch lines is equal to VACTIVE + BP + VSYNC

	pipe_data->pipe_config.subvp_data.prefetch_lines =

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c

+1 −1
Original line number Diff line number Diff line
@@ -281,7 +281,7 @@ static struct timing_generator_funcs dcn32_tg_funcs = { 
		.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,

		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,

		.enable_optc_clock = optc1_enable_optc_clock,

		.set_drr = optc31_set_drr, // TODO: Update to optc32_set_drr once FW headers are promoted

		.set_drr = optc32_set_drr,

		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,

		.set_vtotal_min_max = optc3_set_vtotal_min_max,

		.set_static_screen_control = optc1_set_static_screen_control,

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -2051,6 +2051,7 @@ static bool dcn32_resource_construct( 
	dc->caps.max_cab_allocation_bytes = 67108864; // 64MB = 1024 * 1024 * 64

	dc->caps.subvp_fw_processing_delay_us = 15;

	dc->caps.subvp_prefetch_end_to_mall_start_us = 15;

	dc->caps.subvp_swath_height_margin_lines = 16;

	dc->caps.subvp_pstate_allow_width_us = 20;

	dc->caps.subvp_vertical_int_margin_us = 30;

drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -1662,6 +1662,7 @@ static bool dcn321_resource_construct( 
	dc->caps.max_cab_allocation_bytes = 33554432; // 32MB = 1024 * 1024 * 32

	dc->caps.subvp_fw_processing_delay_us = 15;

	dc->caps.subvp_prefetch_end_to_mall_start_us = 15;

	dc->caps.subvp_swath_height_margin_lines = 16;

	dc->caps.subvp_pstate_allow_width_us = 20;



	dc->caps.max_slave_planes = 1;