Commit 9f4e156c authored by Peter Zijlstra (Intel)'s avatar Peter Zijlstra (Intel) Committed by Zheng Zengkai
Browse files

x86/speculation: Rename RETPOLINE_AMD to RETPOLINE_LFENCE 

stable inclusion
from stable-v5.10.105
commit f38774bb6e231d647d40ceeb8ddf9082eabde667
category: bugfix
bugzilla: 186453 https://gitee.com/src-openeuler/kernel/issues/I50WBM
CVE: CVE-2022-0001

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=f38774bb6e23



--------------------------------

commit d45476d9 upstream.

The RETPOLINE_AMD name is unfortunate since it isn't necessarily
AMD only, in fact Hygon also uses it. Furthermore it will likely be
sufficient for some Intel processors. Therefore rename the thing to
RETPOLINE_LFENCE to better describe what it is.

Add the spectre_v2=retpoline,lfence option as an alias to
spectre_v2=retpoline,amd to preserve existing setups. However, the output
of /sys/devices/system/cpu/vulnerabilities/spectre_v2 will be changed.

  [ bp: Fix typos, massage. ]

Co-developed-by: default avatarJosh Poimboeuf <jpoimboe@redhat.com>
Signed-off-by: default avatarJosh Poimboeuf <jpoimboe@redhat.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Reviewed-by: default avatarThomas Gleixner <tglx@linutronix.de>
[fllinden@amazon.com: backported to 5.10]
Signed-off-by: default avatarFrank van der Linden <fllinden@amazon.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: default avatarChen Jiahao <chenjiahao16@huawei.com>
Reviewed-by: default avatarLiao Chang <liaochang1@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent 50cf2a72

arch/x86/include/asm/cpufeatures.h

+1 −1
Original line number Diff line number Diff line
@@ -204,7 +204,7 @@ 
#define X86_FEATURE_SME			( 7*32+10) /* AMD Secure Memory Encryption */

#define X86_FEATURE_PTI			( 7*32+11) /* Kernel Page Table Isolation enabled */

#define X86_FEATURE_RETPOLINE		( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */

#define X86_FEATURE_RETPOLINE_AMD	( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */

#define X86_FEATURE_RETPOLINE_LFENCE	( 7*32+13) /* "" Use LFENCE for Spectre variant 2 */

#define X86_FEATURE_INTEL_PPIN		( 7*32+14) /* Intel Processor Inventory Number */

#define X86_FEATURE_CDP_L2		( 7*32+15) /* Code and Data Prioritization L2 */

#define X86_FEATURE_MSR_SPEC_CTRL	( 7*32+16) /* "" MSR SPEC_CTRL is implemented */

arch/x86/include/asm/nospec-branch.h

+6 −6
Original line number Diff line number Diff line
@@ -82,7 +82,7 @@ 
#ifdef CONFIG_RETPOLINE

	ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), \

		      __stringify(jmp __x86_retpoline_\reg), X86_FEATURE_RETPOLINE, \

		      __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), X86_FEATURE_RETPOLINE_AMD

		      __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), X86_FEATURE_RETPOLINE_LFENCE

#else

	jmp	*%\reg

#endif
@@ -92,7 +92,7 @@ 
#ifdef CONFIG_RETPOLINE

	ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; call *%\reg), \

		      __stringify(call __x86_retpoline_\reg), X86_FEATURE_RETPOLINE, \

		      __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; call *%\reg), X86_FEATURE_RETPOLINE_AMD

		      __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; call *%\reg), X86_FEATURE_RETPOLINE_LFENCE

#else

	call	*%\reg

#endif
@@ -134,7 +134,7 @@ 
	"lfence;\n"						\

	ANNOTATE_RETPOLINE_SAFE					\

	"call *%[thunk_target]\n",				\

	X86_FEATURE_RETPOLINE_AMD)

	X86_FEATURE_RETPOLINE_LFENCE)



# define THUNK_TARGET(addr) [thunk_target] "r" (addr)
@@ -164,7 +164,7 @@ 
	"lfence;\n"						\

	ANNOTATE_RETPOLINE_SAFE					\

	"call *%[thunk_target]\n",				\

	X86_FEATURE_RETPOLINE_AMD)

	X86_FEATURE_RETPOLINE_LFENCE)



# define THUNK_TARGET(addr) [thunk_target] "rm" (addr)

#endif
@@ -176,8 +176,8 @@ 
/* The Spectre V2 mitigation variants */

enum spectre_v2_mitigation {

	SPECTRE_V2_NONE,

	SPECTRE_V2_RETPOLINE_GENERIC,

	SPECTRE_V2_RETPOLINE_AMD,

	SPECTRE_V2_RETPOLINE,

	SPECTRE_V2_LFENCE,

	SPECTRE_V2_IBRS_ENHANCED,

};

arch/x86/kernel/cpu/bugs.c

+18 −11
Original line number Diff line number Diff line
@@ -627,7 +627,7 @@ enum spectre_v2_mitigation_cmd { 
	SPECTRE_V2_CMD_FORCE,

	SPECTRE_V2_CMD_RETPOLINE,

	SPECTRE_V2_CMD_RETPOLINE_GENERIC,

	SPECTRE_V2_CMD_RETPOLINE_AMD,

	SPECTRE_V2_CMD_RETPOLINE_LFENCE,

};



enum spectre_v2_user_cmd {
@@ -787,8 +787,8 @@ spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) 


static const char * const spectre_v2_strings[] = {

	[SPECTRE_V2_NONE]			= "Vulnerable",

	[SPECTRE_V2_RETPOLINE_GENERIC]		= "Mitigation: Full generic retpoline",

	[SPECTRE_V2_RETPOLINE_AMD]		= "Mitigation: Full AMD retpoline",

	[SPECTRE_V2_RETPOLINE]			= "Mitigation: Retpolines",

	[SPECTRE_V2_LFENCE]			= "Mitigation: LFENCE",

	[SPECTRE_V2_IBRS_ENHANCED]		= "Mitigation: Enhanced IBRS",

};
@@ -800,7 +800,8 @@ static const struct { 
	{ "off",		SPECTRE_V2_CMD_NONE,		  false },

	{ "on",			SPECTRE_V2_CMD_FORCE,		  true  },

	{ "retpoline",		SPECTRE_V2_CMD_RETPOLINE,	  false },

	{ "retpoline,amd",	SPECTRE_V2_CMD_RETPOLINE_AMD,	  false },

	{ "retpoline,amd",	SPECTRE_V2_CMD_RETPOLINE_LFENCE,  false },

	{ "retpoline,lfence",	SPECTRE_V2_CMD_RETPOLINE_LFENCE,  false },

	{ "retpoline,generic",	SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },

	{ "auto",		SPECTRE_V2_CMD_AUTO,		  false },

};
@@ -838,13 +839,19 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) 
	}



	if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||

	     cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||

	     cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||

	     cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&

	    !IS_ENABLED(CONFIG_RETPOLINE)) {

		pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);

		return SPECTRE_V2_CMD_AUTO;

	}



	if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE) &&

	    !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {

		pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n", mitigation_options[i].option);

		return SPECTRE_V2_CMD_AUTO;

	}



	spec_v2_print_cond(mitigation_options[i].option,

			   mitigation_options[i].secure);

	return cmd;
@@ -879,9 +886,9 @@ static void __init spectre_v2_select_mitigation(void) 
		if (IS_ENABLED(CONFIG_RETPOLINE))

			goto retpoline_auto;

		break;

	case SPECTRE_V2_CMD_RETPOLINE_AMD:

	case SPECTRE_V2_CMD_RETPOLINE_LFENCE:

		if (IS_ENABLED(CONFIG_RETPOLINE))

			goto retpoline_amd;

			goto retpoline_lfence;

		break;

	case SPECTRE_V2_CMD_RETPOLINE_GENERIC:

		if (IS_ENABLED(CONFIG_RETPOLINE))
@@ -898,17 +905,17 @@ static void __init spectre_v2_select_mitigation(void) 
retpoline_auto:

	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||

	    boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {

	retpoline_amd:

	retpoline_lfence:

		if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {

			pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");

			goto retpoline_generic;

		}

		mode = SPECTRE_V2_RETPOLINE_AMD;

		setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);

		mode = SPECTRE_V2_LFENCE;

		setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE);

		setup_force_cpu_cap(X86_FEATURE_RETPOLINE);

	} else {

	retpoline_generic:

		mode = SPECTRE_V2_RETPOLINE_GENERIC;

		mode = SPECTRE_V2_RETPOLINE;

		setup_force_cpu_cap(X86_FEATURE_RETPOLINE);

	}

tools/arch/x86/include/asm/cpufeatures.h

+1 −1
Original line number Diff line number Diff line
@@ -204,7 +204,7 @@ 
#define X86_FEATURE_SME			( 7*32+10) /* AMD Secure Memory Encryption */

#define X86_FEATURE_PTI			( 7*32+11) /* Kernel Page Table Isolation enabled */

#define X86_FEATURE_RETPOLINE		( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */

#define X86_FEATURE_RETPOLINE_AMD	( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */

#define X86_FEATURE_RETPOLINE_LFENCE	( 7*32+13) /* "" Use LFENCEs for Spectre variant 2 */

#define X86_FEATURE_INTEL_PPIN		( 7*32+14) /* Intel Processor Inventory Number */

#define X86_FEATURE_CDP_L2		( 7*32+15) /* Code and Data Prioritization L2 */

#define X86_FEATURE_MSR_SPEC_CTRL	( 7*32+16) /* "" MSR SPEC_CTRL is implemented */