Commit 9f4c480f authored by Peter Geis's avatar Peter Geis Committed by Heiko Stuebner
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arm64: dts: rockchip: add rk356x dwc3 usb3 nodes 



Add the dwc3 device nodes to the rk356x device trees.
The rk3566 has one usb2 capable dwc3 otg controller and one usb3 capable
dwc3 host controller.
The rk3568 has one usb3 capable dwc3 otg controller and one usb3 capable
dwc3 host controller.

Signed-off-by: default avatarPeter Geis <pgwipeout@gmail.com>
Tested-by: default avatarFrank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20220408151237.3165046-4-pgwipeout@gmail.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 22a442e6

arch/arm64/boot/dts/rockchip/rk3566.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -6,6 +6,10 @@ 
	compatible = "rockchip,rk3566";

};



&pipegrf {

	compatible = "rockchip,rk3566-pipe-grf", "syscon";

};



&power {

	power-domain@RK3568_PD_PIPE {

		reg = <RK3568_PD_PIPE>;
@@ -18,3 +22,10 @@ 
		#power-domain-cells = <0>;

	};

};



&usb_host0_xhci {

	phys = <&usb2phy0_otg>;

	phy-names = "usb2-phy";

	extcon = <&usb2phy0>;

	maximum-speed = "high-speed";

};

arch/arm64/boot/dts/rockchip/rk3568.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -113,6 +113,10 @@ 
	};

};



&pipegrf {

	compatible = "rockchip,rk3568-pipe-grf", "syscon";

};



&power {

	power-domain@RK3568_PD_PIPE {

		reg = <RK3568_PD_PIPE>;
@@ -128,3 +132,8 @@ 
		#power-domain-cells = <0>;

	};

};



&usb_host0_xhci {

	phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;

	phy-names = "usb2-phy", "usb3-phy";

};

arch/arm64/boot/dts/rockchip/rk356x.dtsi

+34 −1
Original line number Diff line number Diff line
@@ -258,6 +258,40 @@ 
		status = "disabled";

	};



	usb_host0_xhci: usb@fcc00000 {

		compatible = "rockchip,rk3568-dwc3", "snps,dwc3";

		reg = <0x0 0xfcc00000 0x0 0x400000>;

		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,

			 <&cru ACLK_USB3OTG0>;

		clock-names = "ref_clk", "suspend_clk",

			      "bus_clk";

		dr_mode = "host";

		phy_type = "utmi_wide";

		power-domains = <&power RK3568_PD_PIPE>;

		resets = <&cru SRST_USB3OTG0>;

		snps,dis_u2_susphy_quirk;

		status = "disabled";

	};



	usb_host1_xhci: usb@fd000000 {

		compatible = "rockchip,rk3568-dwc3", "snps,dwc3";

		reg = <0x0 0xfd000000 0x0 0x400000>;

		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,

			 <&cru ACLK_USB3OTG1>;

		clock-names = "ref_clk", "suspend_clk",

			      "bus_clk";

		dr_mode = "host";

		phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;

		phy-names = "usb2-phy", "usb3-phy";

		phy_type = "utmi_wide";

		power-domains = <&power RK3568_PD_PIPE>;

		resets = <&cru SRST_USB3OTG1>;

		snps,dis_u2_susphy_quirk;

		status = "disabled";

	};



	gic: interrupt-controller@fd400000 {

		compatible = "arm,gic-v3";

		reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
@@ -325,7 +359,6 @@ 
	};



	pipegrf: syscon@fdc50000 {

		compatible = "rockchip,rk3568-pipe-grf", "syscon";

		reg = <0x0 0xfdc50000 0x0 0x1000>;

	};