Commit 9f007e7b authored by Laurent Pinchart's avatar Laurent Pinchart Committed by Vinod Koul
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dmaengine: xilinx: dpdma: Limit descriptor IDs to 16 bits 



While the descriptor ID is stored in a 32-bit field in the hardware
descriptor, only 16 bits are used by the hardware and are reported
through the XILINX_DPDMA_CH_DESC_ID register. Failure to handle the
wrap-around results in a descriptor ID mismatch after 65536 frames. Fix
it.

Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: default avatarJianqiang Chen <jianqiang.chen@xilinx.com>
Reviewed-by: default avatarJianqiang Chen <jianqiang.chen@xilinx.com>
Link: https://lore.kernel.org/r/20210520152420.23986-5-laurent.pinchart@ideasonboard.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 32828b82

drivers/dma/xilinx/xilinx_dpdma.c

+5 −2
Original line number Diff line number Diff line
@@ -113,6 +113,7 @@ 
#define XILINX_DPDMA_CH_VDO				0x020

#define XILINX_DPDMA_CH_PYLD_SZ				0x024

#define XILINX_DPDMA_CH_DESC_ID				0x028

#define XILINX_DPDMA_CH_DESC_ID_MASK			GENMASK(15, 0)



/* DPDMA descriptor fields */

#define XILINX_DPDMA_DESC_CONTROL_PREEMBLE		0xa5
@@ -866,7 +867,8 @@ static void xilinx_dpdma_chan_queue_transfer(struct xilinx_dpdma_chan *chan) 
	 * will be used, but it should be enough.

	 */

	list_for_each_entry(sw_desc, &desc->descriptors, node)

		sw_desc->hw.desc_id = desc->vdesc.tx.cookie;

		sw_desc->hw.desc_id = desc->vdesc.tx.cookie

				    & XILINX_DPDMA_CH_DESC_ID_MASK;



	sw_desc = list_first_entry(&desc->descriptors,

				   struct xilinx_dpdma_sw_desc, node);
@@ -1086,7 +1088,8 @@ static void xilinx_dpdma_chan_vsync_irq(struct xilinx_dpdma_chan *chan) 
	if (!chan->running || !pending)

		goto out;



	desc_id = dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_ID);

	desc_id = dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_ID)

		& XILINX_DPDMA_CH_DESC_ID_MASK;



	/* If the retrigger raced with vsync, retry at the next frame. */

	sw_desc = list_first_entry(&pending->descriptors,