Commit 9ec30c09 authored by Yong Wu's avatar Yong Wu Committed by Joerg Roedel
Browse files

iommu/mediatek: Add SUB_COMMON_3BITS flag 



In prevous SoC, the sub common id occupy 2 bits. the mt8195's sub common
id has 3bits. Add a new flag for this. and rename the previous flag to
_2BITS. For readable, I put these two flags together, then move the
other flags. no functional change.

Signed-off-by: default avatarYong Wu <yong.wu@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
Link: https://lore.kernel.org/r/20220503071427.2285-16-yong.wu@mediatek.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 82e51771

drivers/iommu/mtk_iommu.c

+16 −10
Original line number Diff line number Diff line
@@ -105,6 +105,8 @@ 
#define REG_MMU1_INT_ID				0x154

#define F_MMU_INT_ID_COMM_ID(a)			(((a) >> 9) & 0x7)

#define F_MMU_INT_ID_SUB_COMM_ID(a)		(((a) >> 7) & 0x3)

#define F_MMU_INT_ID_COMM_ID_EXT(a)		(((a) >> 10) & 0x7)

#define F_MMU_INT_ID_SUB_COMM_ID_EXT(a)		(((a) >> 7) & 0x7)

#define F_MMU_INT_ID_LARB_ID(a)			(((a) >> 7) & 0x7)

#define F_MMU_INT_ID_PORT_ID(a)			(((a) >> 2) & 0x1f)
@@ -116,13 +118,14 @@ 
#define HAS_VLD_PA_RNG			BIT(2)

#define RESET_AXI			BIT(3)

#define OUT_ORDER_WR_EN			BIT(4)

#define HAS_SUB_COMM			BIT(5)

#define WR_THROT_EN			BIT(6)

#define HAS_LEGACY_IVRP_PADDR		BIT(7)

#define IOVA_34_EN			BIT(8)

#define SHARE_PGTABLE			BIT(9) /* 2 HW share pgtable */

#define DCM_DISABLE			BIT(10)

#define STD_AXI_MODE			BIT(11) /* For non MM iommu */

#define HAS_SUB_COMM_2BITS		BIT(5)

#define HAS_SUB_COMM_3BITS		BIT(6)

#define WR_THROT_EN			BIT(7)

#define HAS_LEGACY_IVRP_PADDR		BIT(8)

#define IOVA_34_EN			BIT(9)

#define SHARE_PGTABLE			BIT(10) /* 2 HW share pgtable */

#define DCM_DISABLE			BIT(11)

#define STD_AXI_MODE			BIT(12) /* For non MM iommu */



#define MTK_IOMMU_HAS_FLAG(pdata, _x) \

		((((pdata)->flags) & (_x)) == (_x))
@@ -290,9 +293,12 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 
	fault_pa |= (u64)pa34_32 << 32;



	fault_port = F_MMU_INT_ID_PORT_ID(regval);

	if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) {

	if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM_2BITS)) {

		fault_larb = F_MMU_INT_ID_COMM_ID(regval);

		sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);

	} else if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM_3BITS)) {

		fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval);

		sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval);

	} else {

		fault_larb = F_MMU_INT_ID_LARB_ID(regval);

	}
@@ -1068,7 +1074,7 @@ static const struct mtk_iommu_plat_data mt2712_data = { 


static const struct mtk_iommu_plat_data mt6779_data = {

	.m4u_plat      = M4U_MT6779,

	.flags         = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN,

	.flags         = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN,

	.inv_sel_reg   = REG_MMU_INV_SEL_GEN2,

	.iova_region   = single_domain,

	.iova_region_nr = ARRAY_SIZE(single_domain),
@@ -1105,7 +1111,7 @@ static const struct mtk_iommu_plat_data mt8183_data = { 


static const struct mtk_iommu_plat_data mt8192_data = {

	.m4u_plat       = M4U_MT8192,

	.flags          = HAS_BCLK | HAS_SUB_COMM | OUT_ORDER_WR_EN |

	.flags          = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |

			  WR_THROT_EN | IOVA_34_EN,

	.inv_sel_reg    = REG_MMU_INV_SEL_GEN2,

	.iova_region    = mt8192_multi_dom,

drivers/iommu/mtk_iommu.h

+1 −1
Original line number Diff line number Diff line
@@ -20,7 +20,7 @@ 
#include <dt-bindings/memory/mtk-memory-port.h>



#define MTK_LARB_COM_MAX	8

#define MTK_LARB_SUBCOM_MAX	4

#define MTK_LARB_SUBCOM_MAX	8



#define MTK_IOMMU_GROUP_MAX	8