Commit 9eb77e42 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-meson-v6.5-1' of https://github.com/BayLibre/clk-meson into clk-allwinner 

Pull Amlogic clk driver updates from Jerome Brunet:

 - Add amlogic a1 SoC family PLL and peripheral clock controller support

* tag 'clk-meson-v6.5-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: a1: add Amlogic A1 Peripherals clock controller driver
  clk: meson: a1: add Amlogic A1 PLL clock controller driver
  clk: meson: introduce new pll power-on sequence for A1 SoC family
  clk: meson: make pll rst bit as optional
  dt-bindings: clock: meson: add A1 Peripherals clock controller bindings
  dt-bindings: clock: meson: add A1 PLL clock controller bindings
parents ac9a7868 84af9144

Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/amlogic,a1-peripherals-clkc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic A1 Peripherals Clock Control Unit



maintainers:

  - Neil Armstrong <neil.armstrong@linaro.org>

  - Jerome Brunet <jbrunet@baylibre.com>

  - Jian Hu <jian.hu@jian.hu.com>

  - Dmitry Rokosov <ddrokosov@sberdevices.ru>



properties:

  compatible:

    const: amlogic,a1-peripherals-clkc



  '#clock-cells':

    const: 1



  reg:

    maxItems: 1



  clocks:

    items:

      - description: input fixed pll div2

      - description: input fixed pll div3

      - description: input fixed pll div5

      - description: input fixed pll div7

      - description: input hifi pll

      - description: input oscillator (usually at 24MHz)



  clock-names:

    items:

      - const: fclk_div2

      - const: fclk_div3

      - const: fclk_div5

      - const: fclk_div7

      - const: hifi_pll

      - const: xtal



required:

  - compatible

  - '#clock-cells'

  - reg

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>

    apb {

        #address-cells = <2>;

        #size-cells = <2>;



        clock-controller@800 {

            compatible = "amlogic,a1-peripherals-clkc";

            reg = <0 0x800 0 0x104>;

            #clock-cells = <1>;

            clocks = <&clkc_pll CLKID_FCLK_DIV2>,

                     <&clkc_pll CLKID_FCLK_DIV3>,

                     <&clkc_pll CLKID_FCLK_DIV5>,

                     <&clkc_pll CLKID_FCLK_DIV7>,

                     <&clkc_pll CLKID_HIFI_PLL>,

                     <&xtal>;

            clock-names = "fclk_div2", "fclk_div3",

                          "fclk_div5", "fclk_div7",

                          "hifi_pll", "xtal";

        };

    };

Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic A1 PLL Clock Control Unit



maintainers:

  - Neil Armstrong <neil.armstrong@linaro.org>

  - Jerome Brunet <jbrunet@baylibre.com>

  - Jian Hu <jian.hu@jian.hu.com>

  - Dmitry Rokosov <ddrokosov@sberdevices.ru>



properties:

  compatible:

    const: amlogic,a1-pll-clkc



  '#clock-cells':

    const: 1



  reg:

    maxItems: 1



  clocks:

    items:

      - description: input fixpll_in

      - description: input hifipll_in



  clock-names:

    items:

      - const: fixpll_in

      - const: hifipll_in



required:

  - compatible

  - '#clock-cells'

  - reg

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>

    apb {

        #address-cells = <2>;

        #size-cells = <2>;



        clock-controller@7c80 {

            compatible = "amlogic,a1-pll-clkc";

            reg = <0 0x7c80 0 0x18c>;

            #clock-cells = <1>;

            clocks = <&clkc_periphs CLKID_FIXPLL_IN>,

                     <&clkc_periphs CLKID_HIFIPLL_IN>;

            clock-names = "fixpll_in", "hifipll_in";

        };

    };

MAINTAINERS

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@@ -1888,6 +1888,7 @@ L: linux-amlogic@lists.infradead.org 
S:	Maintained

F:	Documentation/devicetree/bindings/clock/amlogic*

F:	drivers/clk/meson/

F:	include/dt-bindings/clock/a1*

F:	include/dt-bindings/clock/gxbb*

F:	include/dt-bindings/clock/meson*
































drivers/clk/meson/Kconfig



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−0






























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@@ -99,6 +99,26 @@ config COMMON_CLK_AXG_AUDIO







	  Support for the audio clock controller on AmLogic A113D devices,









	  aka axg, Say Y if you want audio subsystem to work.



















config COMMON_CLK_A1_PLL









	tristate "Amlogic A1 SoC PLL controller support"









	depends on ARM64









	select COMMON_CLK_MESON_REGMAP









	select COMMON_CLK_MESON_PLL









	help









	  Support for the PLL clock controller on Amlogic A113L based









	  device, A1 SoC Family. Say Y if you want A1 PLL clock controller









	  to work.



















config COMMON_CLK_A1_PERIPHERALS









	tristate "Amlogic A1 SoC Peripherals clock controller support"









	depends on ARM64









	select COMMON_CLK_MESON_DUALDIV









	select COMMON_CLK_MESON_REGMAP









	help









	  Support for the Peripherals clock controller on Amlogic A113L based









	  device, A1 SoC Family. Say Y if you want A1 Peripherals clock









	  controller to work.



















config COMMON_CLK_G12A









	tristate "G12 and SM1 SoC clock controllers support"









	depends on ARM64
































drivers/clk/meson/Makefile



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@@ -16,6 +16,8 @@ obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o

















obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o









obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o









obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o









obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o









obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o









obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o









obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o