Commit 9e5344e0 authored by Vincenzo Frascino's avatar Vincenzo Frascino Committed by Will Deacon
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arm64: mte: Fix typo in macro definition 



UL in the definition of SYS_TFSR_EL1_TF1 was misspelled causing
compilation issues when trying to implement in kernel MTE async
mode.

Fix the macro correcting the typo.

Note: MTE async mode will be introduced with a future series.

Fixes: c058b1c4 ("arm64: mte: system register definitions")
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: default avatarVincenzo Frascino <vincenzo.frascino@arm.com>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20201130170709.22309-1-vincenzo.frascino@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 2a9b3e6a

arch/arm64/include/asm/sysreg.h

+1 −1
Original line number Diff line number Diff line
@@ -983,7 +983,7 @@ 
#define SYS_TFSR_EL1_TF0_SHIFT	0

#define SYS_TFSR_EL1_TF1_SHIFT	1

#define SYS_TFSR_EL1_TF0	(UL(1) << SYS_TFSR_EL1_TF0_SHIFT)

#define SYS_TFSR_EL1_TF1	(UK(2) << SYS_TFSR_EL1_TF1_SHIFT)

#define SYS_TFSR_EL1_TF1	(UL(1) << SYS_TFSR_EL1_TF1_SHIFT)



/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */

#define SYS_MPIDR_SAFE_VAL	(BIT(31))