Commit 9e4b45f2 authored by Clément Léger's avatar Clément Léger Committed by David S. Miller
Browse files

net: dsa: rzn1-a5psw: enable management frames for CPU port 



Currently, management frame were discarded before reaching the CPU port due
to a misconfiguration of the MGMT_CONFIG register. Enable them by setting
the correct value in this register in order to correctly receive management
frame and handle STP.

Fixes: 888cdb89 ("net: dsa: rzn1-a5psw: add Renesas RZ/N1 advanced 5 port switch driver")
Signed-off-by: default avatarClément Léger <clement.leger@bootlin.com>
Signed-off-by: default avatarAlexis Lothoré <alexis.lothore@bootlin.com>
Reviewed-by: default avatarPiotr Raczynski <piotr.raczynski@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d80fc101

drivers/net/dsa/rzn1_a5psw.c

+1 −1
Original line number Diff line number Diff line
@@ -673,7 +673,7 @@ static int a5psw_setup(struct dsa_switch *ds) 
	}



	/* Configure management port */

	reg = A5PSW_CPU_PORT | A5PSW_MGMT_CFG_DISCARD;

	reg = A5PSW_CPU_PORT | A5PSW_MGMT_CFG_ENABLE;

	a5psw_reg_writel(a5psw, A5PSW_MGMT_CFG, reg);



	/* Set pattern 0 to forward all frame to mgmt port */

drivers/net/dsa/rzn1_a5psw.h

+1 −1
Original line number Diff line number Diff line
@@ -36,7 +36,7 @@ 
#define A5PSW_INPUT_LEARN_BLOCK(p)	BIT(p)



#define A5PSW_MGMT_CFG			0x20

#define A5PSW_MGMT_CFG_DISCARD		BIT(7)

#define A5PSW_MGMT_CFG_ENABLE		BIT(6)



#define A5PSW_MODE_CFG			0x24

#define A5PSW_MODE_STATS_RESET		BIT(31)