Commit 9e3d242f authored by Chin-Yen Lee's avatar Chin-Yen Lee Committed by Kalle Valo
Browse files

wifi: rtw89: pci: correct suspend/resume setting for variant chips 



We find that suspend/resume tests cause 8852CE lost, because some pci
registers are changed for 8852CE. So, correct them accordingly.

Signed-off-by: default avatarChin-Yen Lee <timlee@realtek.com>
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220819064811.37700-6-pkshih@realtek.com
parent 843059d8

drivers/net/wireless/realtek/rtw89/pci.c

+23 −8
Original line number Diff line number Diff line
@@ -3650,14 +3650,20 @@ static int __maybe_unused rtw89_pci_suspend(struct device *dev) 
{

	struct ieee80211_hw *hw = dev_get_drvdata(dev);

	struct rtw89_dev *rtwdev = hw->priv;

	enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;



	rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL,

			  B_AX_PCIE_DIS_L2_CTRL_LDO_HCI);

	rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6);

	rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST);

	rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6);

	if (chip_id == RTL8852A || chip_id == RTL8852B) {

		rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL,

				  B_AX_PCIE_DIS_L2_CTRL_LDO_HCI);

		rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1,

				  B_AX_PCIE_PERST_KEEP_REG | B_AX_PCIE_TRAIN_KEEP_REG);

	} else {

		rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL_V1,

				  B_AX_CMAC_EXIT_L1_EN | B_AX_DMAC0_EXIT_L1_EN);

	}



	return 0;

}
@@ -3678,15 +3684,24 @@ static int __maybe_unused rtw89_pci_resume(struct device *dev) 
{

	struct ieee80211_hw *hw = dev_get_drvdata(dev);

	struct rtw89_dev *rtwdev = hw->priv;

	enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;



	rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL,

			  B_AX_PCIE_DIS_L2_CTRL_LDO_HCI);

	rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6);

	rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST);

	rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6);

	if (chip_id == RTL8852A || chip_id == RTL8852B) {

		rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL,

				  B_AX_PCIE_DIS_L2_CTRL_LDO_HCI);

		rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1,

				  B_AX_PCIE_PERST_KEEP_REG | B_AX_PCIE_TRAIN_KEEP_REG);

	} else {

		rtw89_write32_set(rtwdev, R_AX_PCIE_PS_CTRL_V1,

				  B_AX_CMAC_EXIT_L1_EN | B_AX_DMAC0_EXIT_L1_EN);

		rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL_V1,

				  B_AX_SEL_REQ_ENTR_L1);

	}

	rtw89_pci_l2_hci_ldo(rtwdev);

	rtw89_pci_filter_out(rtwdev);

	rtw89_pci_link_cfg(rtwdev);

	rtw89_pci_l1ss_cfg(rtwdev);