Unverified Commit 9e32f153 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!4356 【OLK-6.6】AMD: support the UMC Performance Counters for Zen4 

Merge Pull Request from: @kile2009 
 
Backporting the patches from the upstream,
https://lore.kernel.org/all/cover.1696425185.git.sandipan.das@amd.com/

issue:
https://gitee.com/openeuler/kernel/issues/I9016O 
 
Link:https://gitee.com/openeuler/kernel/pulls/4356

 

Reviewed-by: default avatarJason Zeng <jason.zeng@intel.com>
Reviewed-by: default avatarXu Kuohai <xukuohai@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parents aab096cc d2857765

arch/x86/events/amd/uncore.c

+694 −366

File changed.

Preview size limit exceeded, changes collapsed.

arch/x86/include/asm/msr-index.h

+4 −0
Original line number Diff line number Diff line
@@ -652,6 +652,10 @@ 
#define MSR_ZEN2_SPECTRAL_CHICKEN	0xc00110e3

#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT	BIT_ULL(1)



/* Fam 19h MSRs */

#define MSR_F19H_UMC_PERF_CTL		0xc0010800

#define MSR_F19H_UMC_PERF_CTR		0xc0010801



/* Fam 17h MSRs */

#define MSR_F17H_IRPERF			0xc00000e9

arch/x86/include/asm/perf_event.h

+9 −0
Original line number Diff line number Diff line
@@ -113,6 +113,13 @@ 
	(AMD64_PERFMON_V2_EVENTSEL_EVENT_NB	|	\

	 AMD64_PERFMON_V2_EVENTSEL_UMASK_NB)



#define AMD64_PERFMON_V2_ENABLE_UMC			BIT_ULL(31)

#define AMD64_PERFMON_V2_EVENTSEL_EVENT_UMC		GENMASK_ULL(7, 0)

#define AMD64_PERFMON_V2_EVENTSEL_RDWRMASK_UMC		GENMASK_ULL(9, 8)

#define AMD64_PERFMON_V2_RAW_EVENT_MASK_UMC		\

	(AMD64_PERFMON_V2_EVENTSEL_EVENT_UMC	|	\

	 AMD64_PERFMON_V2_EVENTSEL_RDWRMASK_UMC)



#define AMD64_NUM_COUNTERS				4

#define AMD64_NUM_COUNTERS_CORE				6

#define AMD64_NUM_COUNTERS_NB				4
@@ -236,6 +243,8 @@ union cpuid_0x80000022_ebx { 
		unsigned int	lbr_v2_stack_sz:6;

		/* Number of Data Fabric Counters */

		unsigned int	num_df_pmc:6;

		/* Number of Unified Memory Controller Counters */

		unsigned int	num_umc_pmc:6;

	} split;

	unsigned int		full;

};

tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json

0 → 100644
+101 −0
Original line number Diff line number Diff line 
[

  {

    "EventName": "umc_mem_clk",

    "PublicDescription": "Number of memory clock cycles.",

    "EventCode": "0x00",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_act_cmd.all",

    "PublicDescription": "Number of ACTIVATE commands sent.",

    "EventCode": "0x05",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_act_cmd.rd",

    "PublicDescription": "Number of ACTIVATE commands sent for reads.",

    "EventCode": "0x05",

    "RdWrMask": "0x1",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_act_cmd.wr",

    "PublicDescription": "Number of ACTIVATE commands sent for writes.",

    "EventCode": "0x05",

    "RdWrMask": "0x2",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_pchg_cmd.all",

    "PublicDescription": "Number of PRECHARGE commands sent.",

    "EventCode": "0x06",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_pchg_cmd.rd",

    "PublicDescription": "Number of PRECHARGE commands sent for reads.",

    "EventCode": "0x06",

    "RdWrMask": "0x1",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_pchg_cmd.wr",

    "PublicDescription": "Number of PRECHARGE commands sent for writes.",

    "EventCode": "0x06",

    "RdWrMask": "0x2",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_cas_cmd.all",

    "PublicDescription": "Number of CAS commands sent.",

    "EventCode": "0x0a",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_cas_cmd.rd",

    "PublicDescription": "Number of CAS commands sent for reads.",

    "EventCode": "0x0a",

    "RdWrMask": "0x1",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_cas_cmd.wr",

    "PublicDescription": "Number of CAS commands sent for writes.",

    "EventCode": "0x0a",

    "RdWrMask": "0x2",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_data_slot_clks.all",

    "PublicDescription": "Number of clocks used by the data bus.",

    "EventCode": "0x14",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_data_slot_clks.rd",

    "PublicDescription": "Number of clocks used by the data bus for reads.",

    "EventCode": "0x14",

    "RdWrMask": "0x1",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_data_slot_clks.wr",

    "PublicDescription": "Number of clocks used by the data bus for writes.",

    "EventCode": "0x14",

    "RdWrMask": "0x2",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  }

]

tools/perf/pmu-events/arch/x86/amdzen4/recommended.json

+84 −0
Original line number Diff line number Diff line
@@ -330,5 +330,89 @@ 
    "MetricGroup": "data_fabric",

    "PerPkg": "1",

    "ScaleUnit": "6.103515625e-5MiB"

  },

  {

    "MetricName": "umc_data_bus_utilization",

    "BriefDescription": "Memory controller data bus utilization.",

    "MetricExpr": "d_ratio(umc_data_slot_clks.all / 2, umc_mem_clk)",

    "MetricGroup": "memory_controller",

    "PerPkg": "1",

    "ScaleUnit": "100%"

  },

  {

    "MetricName": "umc_cas_cmd_rate",

    "BriefDescription": "Memory controller CAS command rate.",

    "MetricExpr": "d_ratio(umc_cas_cmd.all * 1000, umc_mem_clk)",

    "MetricGroup": "memory_controller",

    "PerPkg": "1"

  },

  {

    "MetricName": "umc_cas_cmd_read_ratio",

    "BriefDescription": "Ratio of memory controller CAS commands for reads.",

    "MetricExpr": "d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all)",

    "MetricGroup": "memory_controller",

    "PerPkg": "1",

    "ScaleUnit": "100%"

  },

  {

    "MetricName": "umc_cas_cmd_write_ratio",

    "BriefDescription": "Ratio of memory controller CAS commands for writes.",

    "MetricExpr": "d_ratio(umc_cas_cmd.wr, umc_cas_cmd.all)",

    "MetricGroup": "memory_controller",

    "PerPkg": "1",

    "ScaleUnit": "100%"

  },

  {

    "MetricName": "umc_mem_read_bandwidth",

    "BriefDescription": "Estimated memory read bandwidth.",

    "MetricExpr": "(umc_cas_cmd.rd * 64) / 1e6 / duration_time",

    "MetricGroup": "memory_controller",

    "PerPkg": "1",

    "ScaleUnit": "1MB/s"

  },

  {

    "MetricName": "umc_mem_write_bandwidth",

    "BriefDescription": "Estimated memory write bandwidth.",

    "MetricExpr": "(umc_cas_cmd.wr * 64) / 1e6 / duration_time",

    "MetricGroup": "memory_controller",

    "PerPkg": "1",

    "ScaleUnit": "1MB/s"

  },

  {

    "MetricName": "umc_mem_bandwidth",

    "BriefDescription": "Estimated combined memory bandwidth.",

    "MetricExpr": "(umc_cas_cmd.all * 64) / 1e6 / duration_time",

    "MetricGroup": "memory_controller",

    "PerPkg": "1",

    "ScaleUnit": "1MB/s"

  },

  {

    "MetricName": "umc_cas_cmd_read_ratio",

    "BriefDescription": "Ratio of memory controller CAS commands for reads.",

    "MetricExpr": "d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all)",

    "MetricGroup": "memory_controller",

    "PerPkg": "1",

    "ScaleUnit": "100%"

  },

  {

    "MetricName": "umc_cas_cmd_rate",

    "BriefDescription": "Memory controller CAS command rate.",

    "MetricExpr": "d_ratio(umc_cas_cmd.all * 1000, umc_mem_clk)",

    "MetricGroup": "memory_controller",

    "PerPkg": "1"

  },

  {

    "MetricName": "umc_activate_cmd_rate",

    "BriefDescription": "Memory controller ACTIVATE command rate.",

    "MetricExpr": "d_ratio(umc_act_cmd.all * 1000, umc_mem_clk)",

    "MetricGroup": "memory_controller",

    "PerPkg": "1"

  },

  {

    "MetricName": "umc_precharge_cmd_rate",

    "BriefDescription": "Memory controller PRECHARGE command rate.",

    "MetricExpr": "d_ratio(umc_pchg_cmd.all * 1000, umc_mem_clk)",

    "MetricGroup": "memory_controller",

    "PerPkg": "1"

  }

]