Commit 9e2a0317 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

PCI/ASPM: Factor out L1 PM Substates configuration 

Move L1 PM Substates configuration from pcie_aspm_cap_init() to a new
aspm_l1ss_init() function.  No functional change intended.

Link: https://lore.kernel.org/r/20221005025809.2247547-2-helgaas@kernel.org


Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarKuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
parent 4ff116d0

drivers/pci/pcie/aspm.c

+55 −48
Original line number Diff line number Diff line
@@ -554,13 +554,65 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, 
	aspm_program_l1ss(child, cctl1, ctl2);

}



static void aspm_l1ss_init(struct pcie_link_state *link)

{

	struct pci_dev *child = link->downstream, *parent = link->pdev;

	u32 parent_l1ss_cap, child_l1ss_cap;

	u32 parent_l1ss_ctl1 = 0, child_l1ss_ctl1 = 0;



	/* Setup L1 substate */

	pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,

			      &parent_l1ss_cap);

	pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP,

			      &child_l1ss_cap);



	if (!(parent_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))

		parent_l1ss_cap = 0;

	if (!(child_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))

		child_l1ss_cap = 0;



	/*

	 * If we don't have LTR for the entire path from the Root Complex

	 * to this device, we can't use ASPM L1.2 because it relies on the

	 * LTR_L1.2_THRESHOLD.  See PCIe r4.0, secs 5.5.4, 6.18.

	 */

	if (!child->ltr_path)

		child_l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;



	if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)

		link->aspm_support |= ASPM_STATE_L1_1;

	if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)

		link->aspm_support |= ASPM_STATE_L1_2;

	if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)

		link->aspm_support |= ASPM_STATE_L1_1_PCIPM;

	if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)

		link->aspm_support |= ASPM_STATE_L1_2_PCIPM;



	if (parent_l1ss_cap)

		pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,

				      &parent_l1ss_ctl1);

	if (child_l1ss_cap)

		pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1,

				      &child_l1ss_ctl1);



	if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)

		link->aspm_enabled |= ASPM_STATE_L1_1;

	if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)

		link->aspm_enabled |= ASPM_STATE_L1_2;

	if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)

		link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;

	if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)

		link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;



	if (link->aspm_support & ASPM_STATE_L1SS)

		aspm_calc_l1ss_info(link, parent_l1ss_cap, child_l1ss_cap);

}



static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)

{

	struct pci_dev *child = link->downstream, *parent = link->pdev;

	u32 parent_lnkcap, child_lnkcap;

	u16 parent_lnkctl, child_lnkctl;

	u32 parent_l1ss_cap, child_l1ss_cap;

	u32 parent_l1ss_ctl1 = 0, child_l1ss_ctl1 = 0;

	struct pci_bus *linkbus = parent->subordinate;



	if (blacklist) {
@@ -615,52 +667,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) 
	if (parent_lnkctl & child_lnkctl & PCI_EXP_LNKCTL_ASPM_L1)

		link->aspm_enabled |= ASPM_STATE_L1;



	/* Setup L1 substate */

	pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,

			      &parent_l1ss_cap);

	pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP,

			      &child_l1ss_cap);



	if (!(parent_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))

		parent_l1ss_cap = 0;

	if (!(child_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))

		child_l1ss_cap = 0;



	/*

	 * If we don't have LTR for the entire path from the Root Complex

	 * to this device, we can't use ASPM L1.2 because it relies on the

	 * LTR_L1.2_THRESHOLD.  See PCIe r4.0, secs 5.5.4, 6.18.

	 */

	if (!child->ltr_path)

		child_l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;



	if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)

		link->aspm_support |= ASPM_STATE_L1_1;

	if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)

		link->aspm_support |= ASPM_STATE_L1_2;

	if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)

		link->aspm_support |= ASPM_STATE_L1_1_PCIPM;

	if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)

		link->aspm_support |= ASPM_STATE_L1_2_PCIPM;



	if (parent_l1ss_cap)

		pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,

				      &parent_l1ss_ctl1);

	if (child_l1ss_cap)

		pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1,

				      &child_l1ss_ctl1);



	if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)

		link->aspm_enabled |= ASPM_STATE_L1_1;

	if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)

		link->aspm_enabled |= ASPM_STATE_L1_2;

	if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)

		link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;

	if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)

		link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;



	if (link->aspm_support & ASPM_STATE_L1SS)

		aspm_calc_l1ss_info(link, parent_l1ss_cap, child_l1ss_cap);

	aspm_l1ss_init(link);



	/* Save default state */

	link->aspm_default = link->aspm_enabled;