Commit 9e058c29 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pci-v6.2-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci 

Pull pci fixes from Bjorn Helgaas:

 - Work around apparent firmware issue that made Linux reject MMCONFIG
   space, which broke PCI extended config space (Bjorn Helgaas)

 - Fix CONFIG_PCIE_BT1 dependency due to mid-air collision between a
   PCI_MSI_IRQ_DOMAIN -> PCI_MSI change and addition of PCIE_BT1 (Lukas
   Bulwahn)

* tag 'pci-v6.2-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  x86/pci: Treat EfiMemoryMappedIO as reservation of ECAM space
  x86/pci: Simplify is_mmconf_reserved() messages
  PCI: dwc: Adjust to recent removal of PCI_MSI_IRQ_DOMAIN
parents 92783a90 fd3a8cff

arch/x86/pci/mmconfig-shared.c

+38 −6
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
 */



#include <linux/acpi.h>

#include <linux/efi.h>

#include <linux/pci.h>

#include <linux/init.h>

#include <linux/bitmap.h>
@@ -442,17 +443,42 @@ static bool is_acpi_reserved(u64 start, u64 end, enum e820_type not_used) 
	return mcfg_res.flags;

}



static bool is_efi_mmio(u64 start, u64 end, enum e820_type not_used)

{

#ifdef CONFIG_EFI

	efi_memory_desc_t *md;

	u64 size, mmio_start, mmio_end;



	for_each_efi_memory_desc(md) {

		if (md->type == EFI_MEMORY_MAPPED_IO) {

			size = md->num_pages << EFI_PAGE_SHIFT;

			mmio_start = md->phys_addr;

			mmio_end = mmio_start + size;



			/*

			 * N.B. Caller supplies (start, start + size),

			 * so to match, mmio_end is the first address

			 * *past* the EFI_MEMORY_MAPPED_IO area.

			 */

			if (mmio_start <= start && end <= mmio_end)

				return true;

		}

	}

#endif



	return false;

}



typedef bool (*check_reserved_t)(u64 start, u64 end, enum e820_type type);



static bool __ref is_mmconf_reserved(check_reserved_t is_reserved,

				     struct pci_mmcfg_region *cfg,

				     struct device *dev, int with_e820)

				     struct device *dev, const char *method)

{

	u64 addr = cfg->res.start;

	u64 size = resource_size(&cfg->res);

	u64 old_size = size;

	int num_buses;

	char *method = with_e820 ? "E820" : "ACPI motherboard resources";



	while (!is_reserved(addr, addr + size, E820_TYPE_RESERVED)) {

		size >>= 1;
@@ -464,10 +490,10 @@ static bool __ref is_mmconf_reserved(check_reserved_t is_reserved, 
		return false;



	if (dev)

		dev_info(dev, "MMCONFIG at %pR reserved in %s\n",

		dev_info(dev, "MMCONFIG at %pR reserved as %s\n",

			 &cfg->res, method);

	else

		pr_info(PREFIX "MMCONFIG at %pR reserved in %s\n",

		pr_info(PREFIX "MMCONFIG at %pR reserved as %s\n",

		       &cfg->res, method);



	if (old_size != size) {
@@ -500,7 +526,8 @@ static bool __ref 
pci_mmcfg_check_reserved(struct device *dev, struct pci_mmcfg_region *cfg, int early)

{

	if (!early && !acpi_disabled) {

		if (is_mmconf_reserved(is_acpi_reserved, cfg, dev, 0))

		if (is_mmconf_reserved(is_acpi_reserved, cfg, dev,

				       "ACPI motherboard resource"))

			return true;



		if (dev)
@@ -513,6 +540,10 @@ pci_mmcfg_check_reserved(struct device *dev, struct pci_mmcfg_region *cfg, int e 
			       "MMCONFIG at %pR not reserved in "

			       "ACPI motherboard resources\n",

			       &cfg->res);



		if (is_mmconf_reserved(is_efi_mmio, cfg, dev,

				       "EfiMemoryMappedIO"))

			return true;

	}



	/*
@@ -527,7 +558,8 @@ pci_mmcfg_check_reserved(struct device *dev, struct pci_mmcfg_region *cfg, int e 
	/* Don't try to do this check unless configuration

	   type 1 is available. how about type 2 ?*/

	if (raw_pci_ops)

		return is_mmconf_reserved(e820__mapped_all, cfg, dev, 1);

		return is_mmconf_reserved(e820__mapped_all, cfg, dev,

					  "E820 entry");



	return false;

}

drivers/pci/controller/dwc/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -225,7 +225,7 @@ config PCIE_ARTPEC6_EP 
config PCIE_BT1

	tristate "Baikal-T1 PCIe controller"

	depends on MIPS_BAIKAL_T1 || COMPILE_TEST

	depends on PCI_MSI_IRQ_DOMAIN

	depends on PCI_MSI

	select PCIE_DW_HOST

	help

	  Enables support for the PCIe controller in the Baikal-T1 SoC to work