Commit 9de1f9c8 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'irq-core-2022-08-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq updates from Thomas Gleixner:
 "Updates for interrupt core and drivers:

  Core:

   - Fix a few inconsistencies between UP and SMP vs interrupt
     affinities

   - Small updates and cleanups all over the place

  New drivers:

   - LoongArch interrupt controller

   - Renesas RZ/G2L interrupt controller

  Updates:

   - Hotpath optimization for SiFive PLIC

   - Workaround for broken PLIC edge triggered interrupts

   - Simall cleanups and improvements as usual"

* tag 'irq-core-2022-08-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (52 commits)
  irqchip/mmp: Declare init functions in common header file
  irqchip/mips-gic: Check the return value of ioremap() in gic_of_init()
  genirq: Use for_each_action_of_desc in actions_show()
  irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch
  irqchip: Add LoongArch CPU interrupt controller support
  irqchip: Add Loongson Extended I/O interrupt controller support
  irqchip/loongson-liointc: Add ACPI init support
  irqchip/loongson-pch-msi: Add ACPI init support
  irqchip/loongson-pch-pic: Add ACPI init support
  irqchip: Add Loongson PCH LPC controller support
  LoongArch: Prepare to support multiple pch-pic and pch-msi irqdomain
  LoongArch: Use ACPI_GENERIC_GSI for gsi handling
  genirq/generic_chip: Export irq_unmap_generic_chip
  ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback
  APCI: irq: Add support for multiple GSI domains
  LoongArch: Provisionally add ACPICA data structures
  irqdomain: Use hwirq_max instead of revmap_size for NOMAP domains
  irqdomain: Report irq number for NOMAP domains
  irqchip/gic-v3: Fix comment typo
  dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/V2L SoC
  ...
parents dfea8482 779fda86

Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml

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+134 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)



maintainers:

  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

  - Geert Uytterhoeven <geert+renesas@glider.be>



description: |

  IA55 performs various interrupt controls including synchronization for the external

  interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral

  interrupts output by each IP. And it notifies the interrupt to the GIC

    - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts

    - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts

    - NMI edge select (NMI is not treated as NMI exception and supports fall edge and

      stand-up edge detection interrupts)



allOf:

  - $ref: /schemas/interrupt-controller.yaml#



properties:

  compatible:

    items:

      - enum:

          - renesas,r9a07g044-irqc    # RZ/G2{L,LC}

          - renesas,r9a07g054-irqc    # RZ/V2L

      - const: renesas,rzg2l-irqc



  '#interrupt-cells':

    description: The first cell should contain external interrupt number (IRQ0-7) and the

                 second cell is used to specify the flag.

    const: 2



  '#address-cells':

    const: 0



  interrupt-controller: true



  reg:

    maxItems: 1



  interrupts:

    maxItems: 41



  clocks:

    maxItems: 2



  clock-names:

    items:

      - const: clk

      - const: pclk



  power-domains:

    maxItems: 1



  resets:

    maxItems: 1



required:

  - compatible

  - '#interrupt-cells'

  - '#address-cells'

  - interrupt-controller

  - reg

  - interrupts

  - clocks

  - clock-names

  - power-domains

  - resets



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/r9a07g044-cpg.h>



    irqc: interrupt-controller@110a0000 {

            compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";

            reg = <0x110a0000 0x10000>;

            #interrupt-cells = <2>;

            #address-cells = <0>;

            interrupt-controller;

            interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;

            clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,

                     <&cpg CPG_MOD R9A07G044_IA55_PCLK>;

            clock-names = "clk", "pclk";

            power-domains = <&cpg>;

            resets = <&cpg R9A07G044_IA55_RESETN>;

    };

Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

+60 −5
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@@ -26,9 +26,14 @@ description: 
  with priority below this threshold will not cause the PLIC to raise its

  interrupt line leading to the context.



  While the PLIC supports both edge-triggered and level-triggered interrupts,

  interrupt handlers are oblivious to this distinction and therefore it is not

  specified in the PLIC device-tree binding.

  The PLIC supports both edge-triggered and level-triggered interrupts. For

  edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges

  seen while an interrupt handler is active; the PLIC may either queue them or

  ignore them. In the first case, handlers are oblivious to the trigger type, so

  it is not included in the interrupt specifier. In the second case, software

  needs to know the trigger type, so it can reorder the interrupt flow to avoid

  missing interrupts. This special handling is needed by at least the Renesas

  RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.



  While the RISC-V ISA doesn't specify a memory layout for the PLIC, the

  "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
@@ -47,6 +52,10 @@ maintainers: 
properties:

  compatible:

    oneOf:

      - items:

          - enum:

              - renesas,r9a07g043-plic

          - const: andestech,nceplic100

      - items:

          - enum:

              - sifive,fu540-c000-plic
@@ -64,8 +73,7 @@ properties: 
  '#address-cells':

    const: 0



  '#interrupt-cells':

    const: 1

  '#interrupt-cells': true



  interrupt-controller: true
@@ -82,6 +90,12 @@ properties: 
    description:

      Specifies how many external interrupts are supported by this controller.



  clocks: true



  power-domains: true



  resets: true



required:

  - compatible

  - '#address-cells'
@@ -91,6 +105,47 @@ required: 
  - interrupts-extended

  - riscv,ndev



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - andestech,nceplic100

              - thead,c900-plic



    then:

      properties:

        '#interrupt-cells':

          const: 2



    else:

      properties:

        '#interrupt-cells':

          const: 1



  - if:

      properties:

        compatible:

          contains:

            const: renesas,r9a07g043-plic



    then:

      properties:

        clocks:

          maxItems: 1



        power-domains:

          maxItems: 1



        resets:

          maxItems: 1



      required:

        - clocks

        - power-domains

        - resets



additionalProperties: false



examples:

Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

+15 −0
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@@ -47,6 +47,17 @@ properties: 
  gpio-ranges:

    maxItems: 1



  interrupt-controller: true



  '#interrupt-cells':

    const: 2

    description:

      The first cell contains the global GPIO port index, constructed using the

      RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the

      second cell is used to specify the flag.

      E.g. "interrupts = <RZG2L_GPIO(43, 0) IRQ_TYPE_EDGE_FALLING>;" if P43_0 is

      being used as an interrupt.



  clocks:

    maxItems: 1
@@ -110,6 +121,8 @@ required: 
  - gpio-controller

  - '#gpio-cells'

  - gpio-ranges

  - interrupt-controller

  - '#interrupt-cells'

  - clocks

  - power-domains

  - resets
@@ -126,6 +139,8 @@ examples: 
            gpio-controller;

            #gpio-cells = <2>;

            gpio-ranges = <&pinctrl 0 0 392>;

            interrupt-controller;

            #interrupt-cells = <2>;

            clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;

            resets = <&cpg R9A07G044_GPIO_RSTN>,

                     <&cpg R9A07G044_GPIO_PORT_RESETN>,

arch/alpha/kernel/irq.c

+1 −1
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@@ -60,7 +60,7 @@ int irq_select_affinity(unsigned int irq) 
		cpu = (cpu < (NR_CPUS-1) ? cpu + 1 : 0);

	last_cpu = cpu;



	cpumask_copy(irq_data_get_affinity_mask(data), cpumask_of(cpu));

	irq_data_update_affinity(data, cpumask_of(cpu));

	chip->irq_set_affinity(data, cpumask_of(cpu), false);

	return 0;

}

arch/arm/mach-hisi/Kconfig

+1 −1
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@@ -40,7 +40,7 @@ config ARCH_HIP04 
	select HAVE_ARM_ARCH_TIMER

	select MCPM if SMP

	select MCPM_QUAD_CLUSTER if SMP

	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

	select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP

	help

	  Support for Hisilicon HiP04 SoC family