Commit 9d9ff3d2 authored by Guillaume Ranquet's avatar Guillaume Ranquet Committed by Vinod Koul
Browse files

phy: mediatek: hdmi: mt8195: fix wrong pll calculus 



The clock rate calculus in mtk_hdmi_pll_calc() was wrong when it has
been replaced by 'div_u64'.

Fix the issue by multiplying the values in the denominator instead of
dividing them.

Fixes: 45810d48 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195")
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: default avatarGuillaume Ranquet <granquet@baylibre.com>
Link: https://lore.kernel.org/r/20230413-fixes-for-mt8195-hdmi-phy-v2-2-bbad62e64321@baylibre.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 714dd3c2

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

+2 −2
Original line number Diff line number Diff line
@@ -271,7 +271,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw, 
	 * [32,24] 9bit integer, [23,0]:24bit fraction

	 */

	pcw = div_u64(((u64)ns_hdmipll_ck) << PCW_DECIMAL_WIDTH,

		      da_hdmitx21_ref_ck / PLL_FBKDIV_HS3);

		      da_hdmitx21_ref_ck * PLL_FBKDIV_HS3);



	if (pcw > GENMASK_ULL(32, 0))

		return -EINVAL;
@@ -288,7 +288,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw, 
	posdiv2 = 1;



	/* Digital clk divider, max /32 */

	digital_div = div_u64((u64)ns_hdmipll_ck, posdiv1 / posdiv2 / pixel_clk);

	digital_div = div_u64(ns_hdmipll_ck, posdiv1 * posdiv2 * pixel_clk);

	if (!(digital_div <= 32 && digital_div >= 1))

		return -EINVAL;