drivers/soc/litex: move generic accessors to litex.h (9d93a9e8) · Commits · EulixOS / Software / Kernel

drivers/soc/litex/litex_soc_ctrl.c

+0 −73

Original line number	Diff line number	Diff line
		@@ -16,79 +16,6 @@
		#include <linux/errno.h>
		#include <linux/io.h>

		/*
		* LiteX SoC Generator, depending on the configuration, can split a single
		* logical CSR (Control&Status Register) into a series of consecutive physical
		* registers.
		*
		* For example, in the configuration with 8-bit CSR Bus, 32-bit aligned (the
		* default one for 32-bit CPUs) a 32-bit logical CSR will be generated as four
		* 32-bit physical registers, each one containing one byte of meaningful data.
		*
		* For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus
		*
		* The purpose of `litex_set_reg`/`litex_get_reg` is to implement the logic
		* of writing to/reading from the LiteX CSR in a single place that can be
		* then reused by all LiteX drivers.
		*/

		/**
		* litex_set_reg() - Writes the value to the LiteX CSR (Control&Status Register)
		* @reg: Address of the CSR
		* @reg_size: The width of the CSR expressed in the number of bytes
		* @val: Value to be written to the CSR
		*
		* In the currently supported LiteX configuration (8-bit CSR Bus, 32-bit aligned),
		* a 32-bit LiteX CSR is generated as 4 consecutive 32-bit physical registers,
		* each one containing one byte of meaningful data.
		*
		* This function splits a single possibly multi-byte write into a series of
		* single-byte writes with a proper offset.
		*/
		void litex_set_reg(void __iomem *reg, unsigned long reg_size,
		unsigned long val)
		{
		unsigned long shifted_data, shift, i;

		for (i = 0; i < reg_size; ++i) {
		shift = ((reg_size - i - 1) * LITEX_SUBREG_SIZE_BIT);
		shifted_data = val >> shift;

		WRITE_LITEX_SUBREGISTER(shifted_data, reg, i);
		}
		}
		EXPORT_SYMBOL_GPL(litex_set_reg);

		/**
		* litex_get_reg() - Reads the value of the LiteX CSR (Control&Status Register)
		* @reg: Address of the CSR
		* @reg_size: The width of the CSR expressed in the number of bytes
		*
		* Return: Value read from the CSR
		*
		* In the currently supported LiteX configuration (8-bit CSR Bus, 32-bit aligned),
		* a 32-bit LiteX CSR is generated as 4 consecutive 32-bit physical registers,
		* each one containing one byte of meaningful data.
		*
		* This function generates a series of single-byte reads with a proper offset
		* and joins their results into a single multi-byte value.
		*/
		unsigned long litex_get_reg(void __iomem *reg, unsigned long reg_size)
		{
		unsigned long shifted_data, shift, i;
		unsigned long result = 0;

		for (i = 0; i < reg_size; ++i) {
		shifted_data = READ_LITEX_SUBREGISTER(reg, i);

		shift = ((reg_size - i - 1) * LITEX_SUBREG_SIZE_BIT);
		result \|= (shifted_data << shift);
		}

		return result;
		}
		EXPORT_SYMBOL_GPL(litex_get_reg);

		#define SCRATCH_REG_OFF 0x04
		#define SCRATCH_REG_VALUE 0x12345678
		#define SCRATCH_TEST_VALUE 0xdeadbeef

include/linux/litex.h

+69 −5

Original line number	Diff line number	Diff line
		@@ -3,9 +3,6 @@
		* Common LiteX header providing
		* helper functions for accessing CSRs.
		*
		* Implementation of the functions is provided by
		* the LiteX SoC Controller driver.
		*
		* Copyright (C) 2019-2020 Antmicro <www.antmicro.com>
		*/

		@@ -33,9 +30,76 @@
		#define READ_LITEX_SUBREGISTER(base_offset, subreg_id) \
		le32_to_cpu((__le32 __force)readl(base_offset + (LITEX_REG_SIZE * subreg_id)))

		void litex_set_reg(void __iomem *reg, unsigned long reg_sz, unsigned long val);
		/*
		* LiteX SoC Generator, depending on the configuration, can split a single
		* logical CSR (Control&Status Register) into a series of consecutive physical
		* registers.
		*
		* For example, in the configuration with 8-bit CSR Bus, 32-bit aligned (the
		* default one for 32-bit CPUs) a 32-bit logical CSR will be generated as four
		* 32-bit physical registers, each one containing one byte of meaningful data.
		*
		* For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus
		*
		* The purpose of `litex_set_reg`/`litex_get_reg` is to implement the logic
		* of writing to/reading from the LiteX CSR in a single place that can be
		* then reused by all LiteX drivers.
		*/

		/**
		* litex_set_reg() - Writes the value to the LiteX CSR (Control&Status Register)
		* @reg: Address of the CSR
		* @reg_size: The width of the CSR expressed in the number of bytes
		* @val: Value to be written to the CSR
		*
		* In the currently supported LiteX configuration (8-bit CSR Bus, 32-bit aligned),
		* a 32-bit LiteX CSR is generated as 4 consecutive 32-bit physical registers,
		* each one containing one byte of meaningful data.
		*
		* This function splits a single possibly multi-byte write into a series of
		* single-byte writes with a proper offset.
		*/
		static inline void litex_set_reg(void __iomem *reg, ulong reg_size, ulong val)
		{
		ulong shifted_data, shift, i;

		for (i = 0; i < reg_size; ++i) {
		shift = ((reg_size - i - 1) * LITEX_SUBREG_SIZE_BIT);
		shifted_data = val >> shift;

		WRITE_LITEX_SUBREGISTER(shifted_data, reg, i);
		}
		}

		/**
		* litex_get_reg() - Reads the value of the LiteX CSR (Control&Status Register)
		* @reg: Address of the CSR
		* @reg_size: The width of the CSR expressed in the number of bytes
		*
		* Return: Value read from the CSR
		*
		* In the currently supported LiteX configuration (8-bit CSR Bus, 32-bit aligned),
		* a 32-bit LiteX CSR is generated as 4 consecutive 32-bit physical registers,
		* each one containing one byte of meaningful data.
		*
		* This function generates a series of single-byte reads with a proper offset
		* and joins their results into a single multi-byte value.
		*/
		static inline ulong litex_get_reg(void __iomem *reg, ulong reg_size)
		{
		ulong shifted_data, shift, i;
		ulong result = 0;

		for (i = 0; i < reg_size; ++i) {
		shifted_data = READ_LITEX_SUBREGISTER(reg, i);

		shift = ((reg_size - i - 1) * LITEX_SUBREG_SIZE_BIT);
		result \|= (shifted_data << shift);
		}

		return result;
		}

		unsigned long litex_get_reg(void __iomem *reg, unsigned long reg_sz);

		static inline void litex_write8(void __iomem *reg, u8 val)
		{