Commit 9d61c009 authored by Shawn Guo's avatar Shawn Guo Committed by Chris Ball
Browse files

mmc: sdhci-esdhc-imx: add flag ESDHC_FLAG_USDHC 



Add flag ESDHC_FLAG_USDHC to tell that the ESDHC is actually an USDHC
block, and replace the is_imx6q_usdhc() occurrences with inline function
esdhc_is_usdhc() which checks the flag.

Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
Acked-by: default avatarDong Aisheng <b29396@freescale.com>
Signed-off-by: default avatarChris Ball <cjb@laptop.org>
parent 31fbb301

drivers/mmc/host/sdhci-esdhc-imx.c

+25 −12
Original line number Diff line number Diff line
@@ -89,6 +89,11 @@ 
 * affects i.MX25 and i.MX35.

 */

#define ESDHC_FLAG_ENGCM07207		BIT(2)

/*

 * The flag tells that the ESDHC controller is an USDHC block that is

 * integrated on the i.MX6 series.

 */

#define ESDHC_FLAG_USDHC		BIT(3)



enum imx_esdhc_type {

	IMX25_ESDHC,
@@ -175,6 +180,11 @@ static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 
	return data->devtype == IMX6Q_USDHC;

}



static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)

{

	return !!(data->flags & ESDHC_FLAG_USDHC);

}



static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)

{

	void __iomem *base = host->ioaddr + (reg & ~0x3);
@@ -213,11 +223,11 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 
		}

	}



	if (unlikely(reg == SDHCI_CAPABILITIES_1) && is_imx6q_usdhc(imx_data))

	if (unlikely(reg == SDHCI_CAPABILITIES_1) && esdhc_is_usdhc(imx_data))

		val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104

				| SDHCI_SUPPORT_SDR50;



	if (unlikely(reg == SDHCI_MAX_CURRENT) && is_imx6q_usdhc(imx_data)) {

	if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {

		val = 0;

		val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;

		val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
@@ -307,7 +317,7 @@ static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 


	if (unlikely(reg == SDHCI_HOST_VERSION)) {

		reg ^= 2;

		if (is_imx6q_usdhc(imx_data)) {

		if (esdhc_is_usdhc(imx_data)) {

			/*

			 * The usdhc register returns a wrong host version.

			 * Correct it here.
@@ -321,7 +331,7 @@ static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 
		if (val & ESDHC_VENDOR_SPEC_VSELECT)

			ret |= SDHCI_CTRL_VDD_180;



		if (is_imx6q_usdhc(imx_data)) {

		if (esdhc_is_usdhc(imx_data)) {

			val = readl(host->ioaddr + ESDHC_MIX_CTRL);

			if (val & ESDHC_MIX_CTRL_EXE_TUNE)

				ret |= SDHCI_CTRL_EXEC_TUNING;
@@ -379,7 +389,7 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 
			writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);

		}



		if (is_imx6q_usdhc(imx_data)) {

		if (esdhc_is_usdhc(imx_data)) {

			u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);

			/* Swap AC23 bit */

			if (val & SDHCI_TRNS_AUTO_CMD23) {
@@ -404,7 +414,7 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 
		    (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))

			imx_data->multiblock_status = MULTIBLK_IN_PROCESS;



		if (is_imx6q_usdhc(imx_data))

		if (esdhc_is_usdhc(imx_data))

			writel(val << 16,

			       host->ioaddr + SDHCI_TRANSFER_MODE);

		else
@@ -470,7 +480,7 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 
		 * The reset on usdhc fails to clear MIX_CTRL register.

		 * Do it manually here.

		 */

		if (is_imx6q_usdhc(imx_data))

		if (esdhc_is_usdhc(imx_data))

			writel(0, host->ioaddr + ESDHC_MIX_CTRL);

	}

}
@@ -507,7 +517,7 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 
	u32 temp, val;



	if (clock == 0) {

		if (is_imx6q_usdhc(imx_data)) {

		if (esdhc_is_usdhc(imx_data)) {

			val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);

			writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,

					host->ioaddr + ESDHC_VENDOR_SPEC);
@@ -515,7 +525,7 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 
		goto out;

	}



	if (is_imx6q_usdhc(imx_data))

	if (esdhc_is_usdhc(imx_data))

		pre_div = 1;



	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
@@ -542,7 +552,7 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 
		| (pre_div << ESDHC_PREDIV_SHIFT));

	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);



	if (is_imx6q_usdhc(imx_data)) {

	if (esdhc_is_usdhc(imx_data)) {

		val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);

		writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,

		host->ioaddr + ESDHC_VENDOR_SPEC);
@@ -865,6 +875,9 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 
	if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data))

		imx_data->flags |= ESDHC_FLAG_ENGCM07207;



	if (is_imx6q_usdhc(imx_data))

		imx_data->flags |= ESDHC_FLAG_USDHC;



	imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");

	if (IS_ERR(imx_data->clk_ipg)) {

		err = PTR_ERR(imx_data->clk_ipg);
@@ -917,7 +930,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 
	 * The imx6q ROM code will change the default watermark level setting

	 * to something insane.  Change it back here.

	 */

	if (is_imx6q_usdhc(imx_data))

	if (esdhc_is_usdhc(imx_data))

		writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);



	boarddata = &imx_data->boarddata;
@@ -980,7 +993,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 
	}



	/* sdr50 and sdr104 needs work on 1.8v signal voltage */

	if ((boarddata->support_vsel) && is_imx6q_usdhc(imx_data)) {

	if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data)) {

		imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,

						ESDHC_PINCTRL_STATE_100MHZ);

		imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,