Commit 9d542f7b authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'polarfire-soc-macb-reset-support'

Conor Dooley says:

====================
PolarFire SoC macb reset support

The Cadence MACBs on PolarFire SoC (MPFS) have reset capability and are
compatible with the zynqmp's init function. I have removed the zynqmp
specific comments from that function & renamed it to reflect what it
does, since it is no longer zynqmp only.

MPFS's MACB had previously used the generic binding, so I also added
the required specific binding.

For v2, I noticed some low hanging cleanup fruit so there are extra
patches added for that:
moving the init function out of the config structs, aligning the
alignment of the zynqmp & default config structs with the other dozen
or so structs & simplifing the error paths to use dev_err_probe().

Feel free to apply as many or as few of those as you like.
====================

Link: https://lore.kernel.org/r/20220706095129.828253-1-conor.dooley@microchip.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents a2b6111b 8a78ac73
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+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ properties:
          - enum:
              - cdns,at91sam9260-macb # Atmel at91sam9 SoCs
              - cdns,sam9x60-macb     # Microchip sam9x60 SoC
              - microchip,mpfs-macb   # Microchip PolarFire SoC
          - const: cdns,macb          # Generic

      - items:
+55 −51
Original line number Diff line number Diff line
@@ -4600,6 +4600,40 @@ static int fu540_c000_init(struct platform_device *pdev)
	return macb_init(pdev);
}

static int init_reset_optional(struct platform_device *pdev)
{
	struct net_device *dev = platform_get_drvdata(pdev);
	struct macb *bp = netdev_priv(dev);
	int ret;

	if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
		/* Ensure PHY device used in SGMII mode is ready */
		bp->sgmii_phy = devm_phy_optional_get(&pdev->dev, NULL);

		if (IS_ERR(bp->sgmii_phy))
			return dev_err_probe(&pdev->dev, PTR_ERR(bp->sgmii_phy),
					     "failed to get SGMII PHY\n");

		ret = phy_init(bp->sgmii_phy);
		if (ret)
			return dev_err_probe(&pdev->dev, ret,
					     "failed to init SGMII PHY\n");
	}

	/* Fully reset controller at hardware level if mapped in device tree */
	ret = device_reset_optional(&pdev->dev);
	if (ret) {
		phy_exit(bp->sgmii_phy);
		return dev_err_probe(&pdev->dev, ret, "failed to reset controller");
	}

	ret = macb_init(pdev);
	if (ret)
		phy_exit(bp->sgmii_phy);

	return ret;
}

static const struct macb_usrio_config sama7g5_usrio = {
	.mii = 0,
	.rmii = 1,
@@ -4626,8 +4660,8 @@ static const struct macb_config at91sam9260_config = {
};

static const struct macb_config sama5d3macb_config = {
	.caps = MACB_CAPS_SG_DISABLED
	      | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
	.caps = MACB_CAPS_SG_DISABLED |
		MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
	.clk_init = macb_clk_init,
	.init = macb_init,
	.usrio = &macb_default_usrio,
@@ -4658,8 +4692,8 @@ static const struct macb_config sama5d29_config = {
};

static const struct macb_config sama5d3_config = {
	.caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
	      | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
	.caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE |
		MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
	.dma_burst_length = 16,
	.clk_init = macb_clk_init,
	.init = macb_init,
@@ -4689,55 +4723,13 @@ static const struct macb_config np4_config = {
	.usrio = &macb_default_usrio,
};

static int zynqmp_init(struct platform_device *pdev)
{
	struct net_device *dev = platform_get_drvdata(pdev);
	struct macb *bp = netdev_priv(dev);
	int ret;

	if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
		/* Ensure PS-GTR PHY device used in SGMII mode is ready */
		bp->sgmii_phy = devm_phy_optional_get(&pdev->dev, NULL);

		if (IS_ERR(bp->sgmii_phy)) {
			ret = PTR_ERR(bp->sgmii_phy);
			dev_err_probe(&pdev->dev, ret,
				      "failed to get PS-GTR PHY\n");
			return ret;
		}

		ret = phy_init(bp->sgmii_phy);
		if (ret) {
			dev_err(&pdev->dev, "failed to init PS-GTR PHY: %d\n",
				ret);
			return ret;
		}
	}

	/* Fully reset GEM controller at hardware level using zynqmp-reset driver,
	 * if mapped in device tree.
	 */
	ret = device_reset_optional(&pdev->dev);
	if (ret) {
		dev_err_probe(&pdev->dev, ret, "failed to reset controller");
		phy_exit(bp->sgmii_phy);
		return ret;
	}

	ret = macb_init(pdev);
	if (ret)
		phy_exit(bp->sgmii_phy);

	return ret;
}

static const struct macb_config zynqmp_config = {
	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
		MACB_CAPS_JUMBO |
		MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
	.dma_burst_length = 16,
	.clk_init = macb_clk_init,
	.init = zynqmp_init,
	.init = init_reset_optional,
	.jumbo_max_len = 10240,
	.usrio = &macb_default_usrio,
};
@@ -4751,6 +4743,17 @@ static const struct macb_config zynq_config = {
	.usrio = &macb_default_usrio,
};

static const struct macb_config mpfs_config = {
	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
		MACB_CAPS_JUMBO |
		MACB_CAPS_GEM_HAS_PTP,
	.dma_burst_length = 16,
	.clk_init = macb_clk_init,
	.init = init_reset_optional,
	.usrio = &macb_default_usrio,
	.jumbo_max_len = 10240,
};

static const struct macb_config sama7g5_gem_config = {
	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG |
		MACB_CAPS_MIIONRGMII,
@@ -4787,6 +4790,7 @@ static const struct of_device_id macb_dt_ids[] = {
	{ .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
	{ .compatible = "cdns,zynq-gem", .data = &zynq_config },
	{ .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
	{ .compatible = "microchip,mpfs-macb", .data = &mpfs_config },
	{ .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
	{ .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
	{ /* sentinel */ }