Unverified Commit 9d201b69 authored by Pierre-Louis Bossart's avatar Pierre-Louis Bossart Committed by Mark Brown
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ASoC: SOF: Intel: hda: use BIT() macros for consistency 



BIT() macros should be used for all ADSPIC/IS registers.

Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: default avatarPéter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: default avatarRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20220414184817.362215-12-pierre-louis.bossart@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 406fed80

sound/soc/sof/intel/hda.h

+4 −4
Original line number Diff line number Diff line
@@ -223,8 +223,8 @@ 
#define HDA_DSP_REG_POLL_INTERVAL_US		500	/* 0.5 msec */

#define HDA_DSP_REG_POLL_RETRY_COUNT		50



#define HDA_DSP_ADSPIC_IPC			1

#define HDA_DSP_ADSPIS_IPC			1

#define HDA_DSP_ADSPIC_IPC			BIT(0)

#define HDA_DSP_ADSPIS_IPC			BIT(0)



/* Intel HD Audio General DSP Registers */

#define HDA_DSP_GEN_BASE		0x0
@@ -268,8 +268,8 @@ 
/* HIPCTE */

#define HDA_DSP_REG_HIPCTE_MSG_MASK	0x3FFFFFFF



#define HDA_DSP_ADSPIC_CL_DMA		0x2

#define HDA_DSP_ADSPIS_CL_DMA		0x2

#define HDA_DSP_ADSPIC_CL_DMA		BIT(1)

#define HDA_DSP_ADSPIS_CL_DMA		BIT(1)



/* Delay before scheduling D0i3 entry */

#define BXT_D0I3_DELAY 5000