Commit 9d0c8e79 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm 

Pull KVM fixes from Paolo Bonzini:
 "More fixes for ARM and x86"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
  KVM: LAPIC: Advancing the timer expiration on guest initiated write
  KVM: x86/mmu: Skip !MMU-present SPTEs when removing SP in exclusive mode
  KVM: kvmclock: Fix vCPUs > 64 can't be online/hotpluged
  kvm: x86: annotate RCU pointers
  KVM: arm64: Fix exclusive limit for IPA size
  KVM: arm64: Reject VM creation when the default IPA size is unsupported
  KVM: arm64: Ensure I-cache isolation between vcpus of a same VM
  KVM: arm64: Don't use cbz/adr with external symbols
  KVM: arm64: Fix range alignment when walking page tables
  KVM: arm64: Workaround firmware wrongly advertising GICv2-on-v3 compatibility
  KVM: arm64: Rename __vgic_v3_get_ich_vtr_el2() to __vgic_v3_get_gic_config()
  KVM: arm64: Don't access PMSELR_EL0/PMUSERENR_EL0 when no PMU is available
  KVM: arm64: Turn kvm_arm_support_pmu_v3() into a static key
  KVM: arm64: Fix nVHE hyp panic host context restore
  KVM: arm64: Avoid corrupting vCPU context register in guest exit
  KVM: arm64: nvhe: Save the SPE context early
  kvm: x86: use NULL instead of using plain integer as pointer
  KVM: SVM: Connect 'npt' module param to KVM's internal 'npt_enabled'
  KVM: x86: Ensure deadline timer has truly expired before posting its IRQ
parents 50eb842f 35737d2d

Documentation/virt/kvm/api.rst

+3 −0
Original line number Diff line number Diff line
@@ -182,6 +182,9 @@ is dependent on the CPU capability and the kernel configuration. The limit can 
be retrieved using KVM_CAP_ARM_VM_IPA_SIZE of the KVM_CHECK_EXTENSION

ioctl() at run-time.



Creation of the VM will fail if the requested IPA size (whether it is

implicit or explicit) is unsupported on the host.



Please note that configuring the IPA size does not affect the capability

exposed by the guest CPUs in ID_AA64MMFR0_EL1[PARange]. It only affects

size of the address translated by the stage2 level (guest physical to

arch/arm64/include/asm/kvm_asm.h

+4 −4
Original line number Diff line number Diff line
@@ -47,10 +47,10 @@ 
#define __KVM_HOST_SMCCC_FUNC___kvm_flush_vm_context		2

#define __KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid_ipa		3

#define __KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid		4

#define __KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_local_vmid	5

#define __KVM_HOST_SMCCC_FUNC___kvm_flush_cpu_context		5

#define __KVM_HOST_SMCCC_FUNC___kvm_timer_set_cntvoff		6

#define __KVM_HOST_SMCCC_FUNC___kvm_enable_ssbs			7

#define __KVM_HOST_SMCCC_FUNC___vgic_v3_get_ich_vtr_el2		8

#define __KVM_HOST_SMCCC_FUNC___vgic_v3_get_gic_config		8

#define __KVM_HOST_SMCCC_FUNC___vgic_v3_read_vmcr		9

#define __KVM_HOST_SMCCC_FUNC___vgic_v3_write_vmcr		10

#define __KVM_HOST_SMCCC_FUNC___vgic_v3_init_lrs		11
@@ -183,16 +183,16 @@ DECLARE_KVM_HYP_SYM(__bp_harden_hyp_vecs); 
#define __bp_harden_hyp_vecs	CHOOSE_HYP_SYM(__bp_harden_hyp_vecs)



extern void __kvm_flush_vm_context(void);

extern void __kvm_flush_cpu_context(struct kvm_s2_mmu *mmu);

extern void __kvm_tlb_flush_vmid_ipa(struct kvm_s2_mmu *mmu, phys_addr_t ipa,

				     int level);

extern void __kvm_tlb_flush_vmid(struct kvm_s2_mmu *mmu);

extern void __kvm_tlb_flush_local_vmid(struct kvm_s2_mmu *mmu);



extern void __kvm_timer_set_cntvoff(u64 cntvoff);



extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);



extern u64 __vgic_v3_get_ich_vtr_el2(void);

extern u64 __vgic_v3_get_gic_config(void);

extern u64 __vgic_v3_read_vmcr(void);

extern void __vgic_v3_write_vmcr(u32 vmcr);

extern void __vgic_v3_init_lrs(void);

arch/arm64/include/asm/kvm_hyp.h

+7 −1
Original line number Diff line number Diff line
@@ -83,6 +83,11 @@ void sysreg_restore_guest_state_vhe(struct kvm_cpu_context *ctxt); 
void __debug_switch_to_guest(struct kvm_vcpu *vcpu);

void __debug_switch_to_host(struct kvm_vcpu *vcpu);



#ifdef __KVM_NVHE_HYPERVISOR__

void __debug_save_host_buffers_nvhe(struct kvm_vcpu *vcpu);

void __debug_restore_host_buffers_nvhe(struct kvm_vcpu *vcpu);

#endif



void __fpsimd_save_state(struct user_fpsimd_state *fp_regs);

void __fpsimd_restore_state(struct user_fpsimd_state *fp_regs);
@@ -97,7 +102,8 @@ bool kvm_host_psci_handler(struct kvm_cpu_context *host_ctxt); 


void __noreturn hyp_panic(void);

#ifdef __KVM_NVHE_HYPERVISOR__

void __noreturn __hyp_do_panic(bool restore_host, u64 spsr, u64 elr, u64 par);

void __noreturn __hyp_do_panic(struct kvm_cpu_context *host_ctxt, u64 spsr,

			       u64 elr, u64 par);

#endif



#endif /* __ARM64_KVM_HYP_H__ */

arch/arm64/kernel/image-vars.h

+3 −0
Original line number Diff line number Diff line
@@ -101,6 +101,9 @@ KVM_NVHE_ALIAS(__stop___kvm_ex_table); 
/* Array containing bases of nVHE per-CPU memory regions. */

KVM_NVHE_ALIAS(kvm_arm_hyp_percpu_base);



/* PMU available static key */

KVM_NVHE_ALIAS(kvm_arm_pmu_available);



#endif /* CONFIG_KVM */



#endif /* __ARM64_KERNEL_IMAGE_VARS_H */

arch/arm64/kvm/arm.c

+6 −1
Original line number Diff line number Diff line
@@ -385,11 +385,16 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 
	last_ran = this_cpu_ptr(mmu->last_vcpu_ran);



	/*

	 * We guarantee that both TLBs and I-cache are private to each

	 * vcpu. If detecting that a vcpu from the same VM has

	 * previously run on the same physical CPU, call into the

	 * hypervisor code to nuke the relevant contexts.

	 *

	 * We might get preempted before the vCPU actually runs, but

	 * over-invalidation doesn't affect correctness.

	 */

	if (*last_ran != vcpu->vcpu_id) {

		kvm_call_hyp(__kvm_tlb_flush_local_vmid, mmu);

		kvm_call_hyp(__kvm_flush_cpu_context, mmu);

		*last_ran = vcpu->vcpu_id;

	}