Commit 9cf5b508 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull remoteproc updates from Bjorn Andersson:
 "rproc-virtio device names are now auto generated, to avoid conflicts
  between remoteproc instances.

  The imx_rproc driver is extended with support for communicating with
  and attaching to a running M4 on i.MX8QXP, as well as support for
  attaching to the M4 after self-recovering from a crash. Support is
  added for i.MX8QM and mailbox channels are reconnected during the
  recovery process, in order to avoid data corruption.

  The Xilinx Zynqmp firmware interface is extended and support for the
  Xilinx R5 RPU is introduced.

  Various resources leaks, primarily in error paths, throughout the
  Qualcomm drivers are corrected.

  Lastly a fix to ensure that pm_relax is invoked even if the remoteproc
  instance is stopped between a crash is being reported and the recovery
  handler is scheduled"

* tag 'rproc-v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux: (25 commits)
  remoteproc: core: Do pm_relax when in RPROC_OFFLINE state
  remoteproc: qcom: q6v5: Fix missing clk_disable_unprepare() in q6v5_wcss_qcs404_power_on()
  remoteproc: qcom_q6v5_pas: Fix missing of_node_put() in adsp_alloc_memory_region()
  remoteproc: qcom_q6v5_pas: detach power domains on remove
  remoteproc: qcom_q6v5_pas: disable wakeup on probe fail or remove
  remoteproc: qcom: q6v5: Fix potential null-ptr-deref in q6v5_wcss_init_mmio()
  remoteproc: sysmon: fix memory leak in qcom_add_sysmon_subdev()
  remoteproc: sysmon: Make QMI message rules const
  drivers: remoteproc: Add Xilinx r5 remoteproc driver
  firmware: xilinx: Add RPU configuration APIs
  firmware: xilinx: Add shutdown/wakeup APIs
  firmware: xilinx: Add ZynqMP firmware ioctl enums for RPU configuration.
  arm64: dts: xilinx: zynqmp: Add RPU subsystem device node
  dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings
  remoteproc: core: Use device_match_of_node()
  remoteproc: imx_rproc: Correct i.MX93 DRAM mapping
  remoteproc: imx_rproc: Enable attach recovery for i.MX8QM/QXP
  remoteproc: imx_rproc: Request mbox channel later
  remoteproc: imx_rproc: Support i.MX8QM
  remoteproc: imx_rproc: Support kicking Mcore from Linux for i.MX8QXP
  ...
parents f2855eec 11c7f9e3
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+16 −0
Original line number Diff line number Diff line
@@ -22,6 +22,8 @@ properties:
      - fsl,imx8mn-cm7
      - fsl,imx8mp-cm7
      - fsl,imx8mq-cm4
      - fsl,imx8qm-cm4
      - fsl,imx8qxp-cm4
      - fsl,imx8ulp-cm33
      - fsl,imx93-cm33

@@ -54,12 +56,26 @@ properties:
    minItems: 1
    maxItems: 32

  power-domains:
    maxItems: 8

  fsl,auto-boot:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Indicate whether need to load the default firmware and start the remote
      processor automatically.

  fsl,entry-address:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Specify CPU entry address for SCU enabled processor.

  fsl,resource-id:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      This property is to specify the resource id of the remote processor in SoC
      which supports SCFW

required:
  - compatible

+135 −0
Original line number Diff line number Diff line
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx R5F processor subsystem

maintainers:
  - Ben Levinsky <ben.levinsky@amd.com>
  - Tanmay Shah <tanmay.shah@amd.com>

description: |
  The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
  real-time processing based on the Cortex-R5F processor core from ARM.
  The Cortex-R5F processor implements the Arm v7-R architecture and includes a
  floating-point unit that implements the Arm VFPv3 instruction set.

properties:
  compatible:
    const: xlnx,zynqmp-r5fss

  xlnx,cluster-mode:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1, 2]
    description: |
      The RPU MPCore can operate in split mode (Dual-processor performance), Safety
      lock-step mode(Both RPU cores execute the same code in lock-step,
      clock-for-clock) or Single CPU mode (RPU core 0 is held in reset while
      core 1 runs normally). The processor does not support dynamic configuration.
      Switching between modes is only permitted immediately after a processor reset.
      If set to  1 then lockstep mode and if 0 then split mode.
      If set to  2 then single CPU mode. When not defined, default will be lockstep mode.
      In summary,
      0: split mode
      1: lockstep mode (default)
      2: single cpu mode

patternProperties:
  "^r5f-[a-f0-9]+$":
    type: object
    description: |
      The RPU is located in the Low Power Domain of the Processor Subsystem.
      Each processor includes separate L1 instruction and data caches and
      tightly coupled memories (TCM). System memory is cacheable, but the TCM
      memory space is non-cacheable.

      Each RPU contains one 64KB memory and two 32KB memories that
      are accessed via the TCM A and B port interfaces, for a total of 128KB
      per processor. In lock-step mode, the processor has access to 256KB of
      TCM memory.

    properties:
      compatible:
        const: xlnx,zynqmp-r5f

      power-domains:
        maxItems: 1

      mboxes:
        minItems: 1
        items:
          - description: mailbox channel to send data to RPU
          - description: mailbox channel to receive data from RPU

      mbox-names:
        minItems: 1
        items:
          - const: tx
          - const: rx

      sram:
        $ref: /schemas/types.yaml#/definitions/phandle-array
        minItems: 1
        maxItems: 8
        items:
          maxItems: 1
        description: |
          phandles to one or more reserved on-chip SRAM regions. Other than TCM,
          the RPU can execute instructions and access data from the OCM memory,
          the main DDR memory, and other system memories.

          The regions should be defined as child nodes of the respective SRAM
          node, and should be defined as per the generic bindings in
          Documentation/devicetree/bindings/sram/sram.yaml

      memory-region:
        description: |
          List of phandles to the reserved memory regions associated with the
          remoteproc device. This is variable and describes the memories shared with
          the remote processor (e.g. remoteproc firmware and carveouts, rpmsg
          vrings, ...). This reserved memory region will be allocated in DDR memory.
        minItems: 1
        maxItems: 8
        items:
          - description: region used for RPU firmware image section
          - description: vdev buffer
          - description: vring0
          - description: vring1
        additionalItems: true

    required:
      - compatible
      - power-domains

    unevaluatedProperties: false

required:
  - compatible

additionalProperties: false

examples:
  - |
    remoteproc {
        compatible = "xlnx,zynqmp-r5fss";
        xlnx,cluster-mode = <1>;

        r5f-0 {
            compatible = "xlnx,zynqmp-r5f";
            power-domains = <&zynqmp_firmware 0x7>;
            memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>;
            mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>;
            mbox-names = "tx", "rx";
        };

        r5f-1 {
            compatible = "xlnx,zynqmp-r5f";
            power-domains = <&zynqmp_firmware 0x8>;
            memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, <&rpu1vdev0vring0>, <&rpu1vdev0vring1>;
            mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>;
            mbox-names = "tx", "rx";
        };
    };
...
+33 −0
Original line number Diff line number Diff line
@@ -100,6 +100,22 @@
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		rproc_0_fw_image: memory@3ed00000 {
			no-map;
			reg = <0x0 0x3ed00000 0x0 0x40000>;
		};

		rproc_1_fw_image: memory@3ef00000 {
			no-map;
			reg = <0x0 0x3ef00000 0x0 0x40000>;
		};
	};

	zynqmp_ipi: zynqmp_ipi {
		compatible = "xlnx,zynqmp-ipi-mailbox";
		interrupt-parent = <&gic>;
@@ -203,6 +219,23 @@
		ranges;
	};

	remoteproc {
		compatible = "xlnx,zynqmp-r5fss";
		xlnx,cluster-mode = <1>;

		r5f-0 {
			compatible = "xlnx,zynqmp-r5f";
			power-domains = <&zynqmp_firmware PD_RPU_0>;
			memory-region = <&rproc_0_fw_image>;
		};

		r5f-1 {
			compatible = "xlnx,zynqmp-r5f";
			power-domains = <&zynqmp_firmware PD_RPU_1>;
			memory-region = <&rproc_1_fw_image>;
		};
	};

	amba: axi {
		compatible = "simple-bus";
		#address-cells = <2>;
+97 −0
Original line number Diff line number Diff line
@@ -1166,6 +1166,103 @@ int zynqmp_pm_release_node(const u32 node)
}
EXPORT_SYMBOL_GPL(zynqmp_pm_release_node);

/**
 * zynqmp_pm_get_rpu_mode() - Get RPU mode
 * @node_id:	Node ID of the device
 * @rpu_mode:	return by reference value
 *		either split or lockstep
 *
 * Return:	return 0 on success or error+reason.
 *		if success, then  rpu_mode will be set
 *		to current rpu mode.
 */
int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode)
{
	u32 ret_payload[PAYLOAD_ARG_CNT];
	int ret;

	ret = zynqmp_pm_invoke_fn(PM_IOCTL, node_id,
				  IOCTL_GET_RPU_OPER_MODE, 0, 0, ret_payload);

	/* only set rpu_mode if no error */
	if (ret == XST_PM_SUCCESS)
		*rpu_mode = ret_payload[0];

	return ret;
}
EXPORT_SYMBOL_GPL(zynqmp_pm_get_rpu_mode);

/**
 * zynqmp_pm_set_rpu_mode() - Set RPU mode
 * @node_id:	Node ID of the device
 * @rpu_mode:	Argument 1 to requested IOCTL call. either split or lockstep
 *
 *		This function is used to set RPU mode to split or
 *		lockstep
 *
 * Return:	Returns status, either success or error+reason
 */
int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode)
{
	return zynqmp_pm_invoke_fn(PM_IOCTL, node_id,
				   IOCTL_SET_RPU_OPER_MODE, (u32)rpu_mode,
				   0, NULL);
}
EXPORT_SYMBOL_GPL(zynqmp_pm_set_rpu_mode);

/**
 * zynqmp_pm_set_tcm_config - configure TCM
 * @node_id:	Firmware specific TCM subsystem ID
 * @tcm_mode:	Argument 1 to requested IOCTL call
 *              either PM_RPU_TCM_COMB or PM_RPU_TCM_SPLIT
 *
 * This function is used to set RPU mode to split or combined
 *
 * Return: status: 0 for success, else failure
 */
int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode)
{
	return zynqmp_pm_invoke_fn(PM_IOCTL, node_id,
				   IOCTL_TCM_COMB_CONFIG, (u32)tcm_mode, 0,
				   NULL);
}
EXPORT_SYMBOL_GPL(zynqmp_pm_set_tcm_config);

/**
 * zynqmp_pm_force_pwrdwn - PM call to request for another PU or subsystem to
 *             be powered down forcefully
 * @node:  Node ID of the targeted PU or subsystem
 * @ack:   Flag to specify whether acknowledge is requested
 *
 * Return: status, either success or error+reason
 */
int zynqmp_pm_force_pwrdwn(const u32 node,
			   const enum zynqmp_pm_request_ack ack)
{
	return zynqmp_pm_invoke_fn(PM_FORCE_POWERDOWN, node, ack, 0, 0, NULL);
}
EXPORT_SYMBOL_GPL(zynqmp_pm_force_pwrdwn);

/**
 * zynqmp_pm_request_wake - PM call to wake up selected master or subsystem
 * @node:  Node ID of the master or subsystem
 * @set_addr:  Specifies whether the address argument is relevant
 * @address:   Address from which to resume when woken up
 * @ack:   Flag to specify whether acknowledge requested
 *
 * Return: status, either success or error+reason
 */
int zynqmp_pm_request_wake(const u32 node,
			   const bool set_addr,
			   const u64 address,
			   const enum zynqmp_pm_request_ack ack)
{
	/* set_addr flag is encoded into 1st bit of address */
	return zynqmp_pm_invoke_fn(PM_REQUEST_WAKEUP, node, address | set_addr,
				   address >> 32, ack, NULL);
}
EXPORT_SYMBOL_GPL(zynqmp_pm_request_wake);

/**
 * zynqmp_pm_set_requirement() - PM call to set requirement for PM slaves
 * @node:		Node ID of the slave
+13 −0
Original line number Diff line number Diff line
@@ -352,6 +352,19 @@ config TI_K3_R5_REMOTEPROC
	  It's safe to say N here if you're not interested in utilizing
	  a slave processor.

config XLNX_R5_REMOTEPROC
	tristate "Xilinx R5 remoteproc support"
	depends on PM && ARCH_ZYNQMP
	select ZYNQMP_FIRMWARE
	select RPMSG_VIRTIO
	select MAILBOX
	select ZYNQMP_IPI_MBOX
	help
	  Say y or m here to support Xilinx R5 remote processors via the remote
	  processor framework.

	  It's safe to say N if not interested in using RPU r5f cores.

endif # REMOTEPROC

endmenu
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