Commit 9cea0d46 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branch 'x86/cpu' into x86/core, to resolve conflicts 



Conflicts:
	arch/x86/include/asm/cpufeatures.h

Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents 8c490b42 08f253ec

Documentation/ABI/stable/sysfs-devices-system-cpu

+4 −0
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@@ -86,6 +86,10 @@ What: /sys/devices/system/cpu/cpuX/topology/die_cpus 
Description:    internal kernel map of CPUs within the same die.

Description:    internal kernel map of CPUs within the same die.

Values:         hexadecimal bitmask.

Values:         hexadecimal bitmask.





What:           /sys/devices/system/cpu/cpuX/topology/ppin

Description:    per-socket protected processor inventory number

Values:         hexadecimal.



What:           /sys/devices/system/cpu/cpuX/topology/die_cpus_list

What:           /sys/devices/system/cpu/cpuX/topology/die_cpus_list

Description:    human-readable list of CPUs within the same die.

Description:    human-readable list of CPUs within the same die.

                The format is like 0-3, 8-11, 14,17.

                The format is like 0-3, 8-11, 14,17.

Documentation/ABI/testing/sysfs-devices-system-cpu

+6 −0
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@@ -73,6 +73,7 @@ What: /sys/devices/system/cpu/cpuX/topology/core_id 
		/sys/devices/system/cpu/cpuX/topology/physical_package_id

		/sys/devices/system/cpu/cpuX/topology/physical_package_id

		/sys/devices/system/cpu/cpuX/topology/thread_siblings

		/sys/devices/system/cpu/cpuX/topology/thread_siblings

		/sys/devices/system/cpu/cpuX/topology/thread_siblings_list

		/sys/devices/system/cpu/cpuX/topology/thread_siblings_list

		/sys/devices/system/cpu/cpuX/topology/ppin

Date:		December 2008

Date:		December 2008

Contact:	Linux kernel mailing list <linux-kernel@vger.kernel.org>

Contact:	Linux kernel mailing list <linux-kernel@vger.kernel.org>

Description:	CPU topology files that describe a logical CPU's relationship

Description:	CPU topology files that describe a logical CPU's relationship
@@ -103,6 +104,11 @@ Description: CPU topology files that describe a logical CPU's relationship 
		thread_siblings_list: human-readable list of cpuX's hardware

		thread_siblings_list: human-readable list of cpuX's hardware

		threads within the same core as cpuX

		threads within the same core as cpuX





		ppin: human-readable Protected Processor Identification

		Number of the socket the cpu# belongs to. There should be

		one per physical_package_id. File is readable only to

		admin.



		See Documentation/admin-guide/cputopology.rst for more information.

		See Documentation/admin-guide/cputopology.rst for more information.

arch/x86/include/asm/cpufeatures.h

+3 −3
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@@ -299,9 +299,6 @@ 
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */

/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */

#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */

#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */

#define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */

#define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */

#define X86_FEATURE_AMX_BF16		(18*32+22) /* AMX bf16 Support */

#define X86_FEATURE_AMX_TILE		(18*32+24) /* AMX tile Support */

#define X86_FEATURE_AMX_INT8		(18*32+25) /* AMX int8 Support */





/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */

/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */

#define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */

#define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
@@ -391,7 +388,10 @@ 
#define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */

#define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */

#define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */

#define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */

#define X86_FEATURE_IBT			(18*32+20) /* Indirect Branch Tracking */

#define X86_FEATURE_IBT			(18*32+20) /* Indirect Branch Tracking */

#define X86_FEATURE_AMX_BF16		(18*32+22) /* AMX bf16 Support */

#define X86_FEATURE_AVX512_FP16		(18*32+23) /* AVX512 FP16 */

#define X86_FEATURE_AVX512_FP16		(18*32+23) /* AVX512 FP16 */

#define X86_FEATURE_AMX_TILE		(18*32+24) /* AMX tile Support */

#define X86_FEATURE_AMX_INT8		(18*32+25) /* AMX int8 Support */

#define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */

#define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */

#define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */

#define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */

#define X86_FEATURE_FLUSH_L1D		(18*32+28) /* Flush L1D cache */

#define X86_FEATURE_FLUSH_L1D		(18*32+28) /* Flush L1D cache */

arch/x86/include/asm/processor.h

+2 −0
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@@ -119,6 +119,8 @@ struct cpuinfo_x86 { 
	int			x86_cache_mbm_width_offset;

	int			x86_cache_mbm_width_offset;

	int			x86_power;

	int			x86_power;

	unsigned long		loops_per_jiffy;

	unsigned long		loops_per_jiffy;

	/* protected processor identification number */

	u64			ppin;

	/* cpuid returned max cores value: */

	/* cpuid returned max cores value: */

	u16			x86_max_cores;

	u16			x86_max_cores;

	u16			apicid;

	u16			apicid;

arch/x86/include/asm/topology.h

+1 −0
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@@ -110,6 +110,7 @@ extern const struct cpumask *cpu_clustergroup_mask(int cpu); 
#define topology_logical_die_id(cpu)		(cpu_data(cpu).logical_die_id)

#define topology_logical_die_id(cpu)		(cpu_data(cpu).logical_die_id)

#define topology_die_id(cpu)			(cpu_data(cpu).cpu_die_id)

#define topology_die_id(cpu)			(cpu_data(cpu).cpu_die_id)

#define topology_core_id(cpu)			(cpu_data(cpu).cpu_core_id)

#define topology_core_id(cpu)			(cpu_data(cpu).cpu_core_id)

#define topology_ppin(cpu)			(cpu_data(cpu).ppin)





extern unsigned int __max_die_per_package;

extern unsigned int __max_die_per_package;