Commit 9cd5f2ce authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/rcar'

- Remove unused static pcie_base and pcie_dev (Geert Uytterhoeven)

* pci/controller/rcar:
  PCI: rcar: Use correct product family name for Renesas R-Car
  PCI: rcar-host: Remove unused static pcie_base and pcie_dev
parents 5c13b3c1 e28e75e9
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+2 −23
Original line number Diff line number Diff line
@@ -41,21 +41,6 @@ struct rcar_msi {
	int irq2;
};

#ifdef CONFIG_ARM
/*
 * Here we keep a static copy of the remapped PCIe controller address.
 * This is only used on aarch32 systems, all of which have one single
 * PCIe controller, to provide quick access to the PCIe controller in
 * the L1 link state fixup function, called from the ARM fault handler.
 */
static void __iomem *pcie_base;
/*
 * Static copy of PCIe device pointer, so we can check whether the
 * device is runtime suspended or not.
 */
static struct device *pcie_dev;
#endif

/* Structure representing the PCIe interface */
struct rcar_pcie_host {
	struct rcar_pcie	pcie;
@@ -684,7 +669,7 @@ static void rcar_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
}

static struct irq_chip rcar_msi_bottom_chip = {
	.name			= "Rcar MSI",
	.name			= "R-Car MSI",
	.irq_ack		= rcar_msi_irq_ack,
	.irq_mask		= rcar_msi_irq_mask,
	.irq_unmask		= rcar_msi_irq_unmask,
@@ -813,7 +798,7 @@ static int rcar_pcie_enable_msi(struct rcar_pcie_host *host)

	/*
	 * Setup MSI data target using RC base address address, which
	 * is guaranteed to be in the low 32bit range on any RCar HW.
	 * is guaranteed to be in the low 32bit range on any R-Car HW.
	 */
	rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR);
	rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR);
@@ -879,12 +864,6 @@ static int rcar_pcie_get_resources(struct rcar_pcie_host *host)
	}
	host->msi.irq2 = i;

#ifdef CONFIG_ARM
	/* Cache static copy for L1 link state fixup hook on aarch32 */
	pcie_base = pcie->base;
	pcie_dev = pcie->dev;
#endif

	return 0;

err_irq2: